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Ixiasoft
4.9.2. Power Distribution System
Figure 15. Power Distribution System Block Diagram
Power Source Name | Power Name | Maximum Output Current (A) | Description |
---|---|---|---|
LTC3884 (U44) | VCC (0.85V) VCCP (0.85V) |
132 | Core Logic Power Periphery Power |
EM2120L (U51) | VCCIO_UIB (1.2V) | 12 | Power for HBM’s Universal Interface Block |
EN63A0 (U46) | S10_VCCERAM (0.9V) VCCPLLDIG_SDM (0.9V) |
4.6 | Embedded memory and digital transceiver power |
EN63A0 (U49) | S10_VCCT_GXB (1.12V) | 2.1 | Transmitter Power |
EN63A0 (U48) | S10_VCCRR_GXB (1.12V) | 4.0 | Receiver Power Right side |
EN63A0 (U47) | S10_VCCRL_GXB (1.12V) | 4.0 | Receiver Power Left side |
EN63A0 (U50) | VCCH_GXB(1.8V) VCCADC (1.8V) VCCA_PLL (1.8V) VCC_PLL_SDM (1.8V) VCCPT (1.8V) VCCBAT (1.8V) VCCIO_SDM (1.8V) VCCIO (1.8v) |
11 |
Analog power for Receivers ADC power PLL Analog Global power PLL Power to SDM block Charge-pump power Battery Back-up power for encryption key Configuration pins power IO Power |
LTM4625 (U40) | 5V | 5.0 | System 5V Rail |
EY1501 (U41) | 3V3_STBY (3.3V) | ||
EY1501 (U42) | 1p8V_PRE_STBY (1.8V) | ||
EN6337 (U58) | 2p5V (2.5V) DDR4_VCCP (2.5V) DDR4_VCCSPD (2.5V) |
1.0 | System 2.5V Rail |
EN6362 (U57) | HiLo VDD (1.25V/1.30V/1.35V/1.5V) | 6.0 | VDD power for HiLo |
EN6362 (U56) | HiLo VDDQ (1.25V/1.30V/1.35V/1.5V) | 2.0 | VDDQ power for HiLo |
EN6360 (U60) | VCCM (2.5V) | 2.6 | Embedded HBM2 memory power |
EM2130H(U43) | 3p3V (3.3V) | 30 | System 3.3V rail |
TPS51200 (U54) | 0p6V_DDR4_DIMM_VTT (0.6V) | 1mA | Termination power for DIMM |
TPS51200 (U55) | 0p6V_DDR4_COMP_VTT (0.6V) | 1mA | Termination power for on-board DDR4 |
12V_G1, 12V_G2 | 12V | 20 | System 12V rail |