Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6.5. I2C

I2C supports communication between integrated circuits on a board. It is a simple two-wire bus that consists of a serial data line (SDA) and a serial clock (SCL). The Intel® MAX® 10 and the Intel® Stratix® 10 devices use the I2C for reading and writing to the various components on the board such as programmable clock generators, VID regulators, ADC and temperature sensors. You can use the Intel® Stratix® 10 or Intel® MAX® 10 as the I2C host to access these devices, change clock frequencies or get status information of the board such as voltage and temperature readings.

Figure 11. I2C Block Diagram
Table 19.   Intel® MAX® 10 I2C Signals
Schematic Signal Name Intel® MAX® 10 Pin Number I/O Standard Description
MAIN_I2C_SCL F8 1.8 V I2C serial clock from Intel® MAX® 10 (U24)
MAIN_I2C_SDA B12 1.8 V

I2C serial data from Intel® MAX® 10

(U24)
PCIE_EP_3V3_I2C_SCL K1 3.3 V

I2C serial clock from Intel® MAX® 10

(U24)
PCIE_EP_3V3_I2C_SDA L2 3.3 V

I2C serial data from Intel® MAX® 10

(U24)
I2C_3V3_SCL N9 3.3 V

I2C serial data from Intel® MAX® 10

(U27)
I2C_3V3_SDA M12 3.3 V

I2C serial data from Intel® MAX® 10

(U27)
Table 20.   Intel® Stratix® 10 MX FPGA I2C Signals
Schematic Signal Name Intel® Stratix® 10 MX FPGA Pin Number I/O Standard Description
S10_SDM_SCL BA38 1.8V Intel® Stratix® 10 FPGA I2C from SDM IO pin (default)
S10_SDM_SDA AW38 1.8V Intel® Stratix® 10 FPGA I2C from SDM IO pin (default)
DDR4_DIMM_SCL H30 1.8V Intel® Stratix® 10 FPGA I2C from GPIO pin
DDR4_DIMM_SDA D29 1.8V Intel® Stratix® 10 FPGA I2C from GPIO pin
Table 21.   Intel® Stratix® 10 MX FPGA I2C Signals to Intel® MAX® 10 Intel® FPGA Download Cable II
Schematic Signal Name Intel® Stratix® 10 MX FPGA Pin Number I/O Standard Description
MAIN_I2C_SCL BE14 1.8V Not connected by default
MAIN_I2C_SDA BF13 1.8V Not connected by default
Table 22.   Intel® Stratix® 10 MX FPGA I2C Signals to QSFP Module
Schematic Signal Names Intel® Stratix® 10 MX FPGA Pin Number I/O Standard Description
ZQSFP_S10_I2C_SCL BJ16 1.8V Intel® Stratix® 10 FPGA I2C from GPIO pin
ZQSFP_S10_I2C_SDA BD16 1.8V Intel® Stratix® 10 FPGA I2C from GPIO pin
Table 23.   Intel® Stratix® 10 MX FPGA I2C Signals to PCIe End Point Connector
Schematic Signal Name Intel® Stratix® 10 MX FPGA Pin Number PCIe Connector (J6) Pin Number I/O Standard Description
PCIE_EP_I2C_SCL BH15 B5 1.8V Via U10 Dedicated I2C to PCIe Connector
PCIE_EP_I2C_SDA BH14 B6 1.8V Via U10 Dedicated I2C to PCIe Connector
Table 24.  I2C Device Address
Type Address Device
Intel® Stratix® 10 MX FPGA I2C Address 0xA0 DDR4 DIMM (J1)
0x47 LTC3884
0x20 Intel® MAX® 10 Power (U27)
0x4C MAX1619 (U28)
0x4E EM2130H (U43)
0x31 EM2120H (U51)
TBD QSFP0 (J5)
TBD QSFP1 (J4)
TBD PCIe Root Port (J7)
TBD PCIe End Point (J6)
Intel® MAX® 10 I2C Address 0x74 Si5338A (U16)
0x70 Si5338A (U18)
0x73 Si5342 (U19)
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