Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6.3. High Bandwidth Memory (HBM2)

The integrated 3D stack High-Bandwidth DRAM Memory (HBM2) is a "near memory" implementation where the high-density stacked DRAM is integrated very close to the FPGA in the same package.

In this configuration, the in-package memory is able to deliver up to 512 GBps of total aggregate bandwidth which represents over 10 times increase in bandwidth compared to traditional "far memory" implemented in separate devices on the board.

The Intel® Stratix® 10 MX FPGA on this development kit has two 4 GB on-package 3D stacked HBM2 DRAM memories. Each of these DRAM stacks has:
  • 8 GB total density (4 GB x2)
  • 256 GB/sec total aggregate bandwidth
  • 8 independent channels, each 128 bit wide
  • Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
  • Full-rate transfer to core fabric
There are two Universal Interface Blocks (UIB).
  • CLK_UIB0_N/P: programmable LVDS clock inputs to UIB tiles 0 of the device.
  • CLK_UIB1_N/P: programmable LVDS clock inputs to UIB tiles 1 of the device.
  • 240 Ohm 1% external reference resistors
  • Test points on top-side of the board for ATB nodes access
  • atb0/atb1/atb2/atb3 - Each UIB has four ATB test points.
ESRAM has the following pins:
  • CLK_ESRAM0_N/P: LVDS input reference clock for ESRAM Block0
  • CLK_ESRAM1_N/P: LVDS input reference clock for ESRAM Block1
  • 2K Ohm 1% external reference resistors
  • atb0/atb1 – access pads for probing
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