Visible to Intel only — GUID: vzx1614084258372
Ixiasoft
Visible to Intel only — GUID: vzx1614084258372
Ixiasoft
1. About the F-Tile Interlaken Intel® FPGA IP
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 8.1.0 |
Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.
Interlaken look-aside is a scalable protocol that allows interoperability between a datapath device and a look-aside co-processor with packet transfer rates up to 300 Gbps. The IP supports Interlaken look-aside