F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

1.1. F-Tile Interlaken IP Features

General features

  • Compliant with the Interlaken Protocol Specification, Revision 1.2.
  • Compliant with the Interlaken Reed-Solomon Forward Error Correction (RS-FEC) Extension Specification, Revision 1.1.
  • Support for 1, 2, 3, 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 675 Gbps raw bandwidth. Refer to the IP Supported Combinations of Number of Lanes and Data Rates for more details on supported configurations.
  • Support forper-lane data rates of 6.25, 10.3125, 12.5, 25.78125, 53.125, 56.25, and 106.25 Gbps using the Intel FPGA on-chip high-speed transceivers.
  • All variants have support for the Interlaken look-aside feature.

User interface features

  • Dynamically configurable BurstMax and BurstMin values.
  • Packet mode and Interleaved mode for user data transfer.
  • Up to 256 logical channels in out-of-the-box configuration.
  • Multisegment user interface.

Flow-control features

  • Optional out-of-band flow control blocks.
  • Optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
  • Error correction code (ECC) for memory block implementation with the IP.

Line-side features

  • Per-lane data rate of 53.125 and 56.25 Gbps using pulse amplitude modulation (PAM4) FGT PMAs and 106.25 Gbps using the PAM4 FHT PMAs.
  • Per lane data rates of 6.25, 10.3125, 12.5, 25.78125 Gbps using non-return-to-zero (NRZ) mode.
Table 1.  IP Supported Physical Combinations of Number of Lanes and Data RatesThe IP supports the following combinations in the Quartus® Prime Pro Edition software version 24.2.

For FGT PAM4 transceiver mode:

  • Physical configuration of 2 lanes x 53.125 Gbps, corresponds to IP GUI settings 4 lanes x 26.5625 Gbps.
  • Physical configuration of 10 lanes x 56.25 Gbps, corresponding to IP GUI settings 20 lanes x 28.125 Gbps.
For FHT PAM4 transceiver mode:
  • Physical configuration of 1 lane x 106.25 Gbps, corresponds to IP GUI settings 4 lanes x 26.5625 Gbps.
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.78125 53.125 56.25 106.25
1 - - - - - - Yes
2 - - - - Yes - Yes
3 - - - - - - Yes
4 Yes - Yes Yes Yes - Yes
6 - - - Yes Yes - -
8 - Yes Yes Yes Yes - -
101 - - Yes Yes Yes Yes -
12 - Yes Yes Yes Yes Yes -
Table 2.  IP Theoretical Raw Aggregate BandwidthThe IP supports supports the following combinations in the Quartus® Prime Pro Edition software version 24.1
PMA Type Lane Rate (Gbps) Number of Lanes User Interface Width (words) Data Width (bits) Raw Aggregate Bandwidth (Gbps)
FGT 6.25 4 4 256 25
10.3125 8 8 512 82.5
12 8 512 123.75
12.5 4 4 256 50
8 8 512 100
10 8 512 125
12 8 512 150
25.78125 4 4 256 103.125
6 8 512 154.6875
8 8 512 206.25
10 16 1024 257.8125
12 16 1024 309.375
53.125 2 4 256 106.25
4 8 512 212.5
6 16 1024 318.75
8 16 1024 425
10 16 1024 531.25
12 32 2048 637.5
56.25 10 16 1024 562.5
12 32 2048 675
FHT 106.25 1 4 256 106.25
2 8 512 212.5
3 16 1024 318.75
4 16 1024 425
1 For a 10-lane configuration design, the F-Tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew.
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