F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

1.4. F-Tile Interlaken IP Performance and Resources

The tables show the resources and expected performance for selected variations of the Interlaken IP using the Quartus® Prime Pro Edition software version 24.2. Your results may slightly vary depending on the device you select. The tables show Data rate and the Number of lanes that you select in the GUI, which is different than the physical data rate and number of lanes.

For a list of supported configurations, refer to IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved Mode (number of segments = 1)
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18,937.5 46,476 7,952 28
10.3125 8 39,080.3 82,507 13,794 52
12 60,196.4 119,313 19,459 73
12.5 4 18,959.1 46,453 7,926 28
8 39,059.6 82,367 14,131 52
10 49,557.7 101,269 16,213 61
12 60,179.2 119,723 19,167 73
25.78125 4 19,309.5 46,859 8,516 28
6 30,680.2 69,638 11,932 52
8 39,584.1 83,557 14,529 52
10 54,708.7 117,521 18,397 100
12 64,627.4 134,013 21,647 100
PAM4 FGT 26.5625 4 18,906.1 50,865 9,098 28
4 2 19,104.4 50,630 9,375 28
8 38,310.3 90,617 16,397 52
8 2 38,741.7 90,797 16,193 52
12 63,154.7 144,989 23,681 100
12 2 63,643.2 144,425 24,175 100
16 83,765.2 187,568 31,450 100
162 85,095.1 187,489 31,037 100
20 108,465.3 238,826 38,338 121
20 2 110,160.2 238,900 37,829 121
244 135,177.0 297,176 44,550 148
242 4 137,202.8 297,737 45,367 148
24 3 142,625.1 318,411 47,035 196
242 3 144,799.1 317,551 47,733 196
28.125 20 109,182.5 238,809 37,859 121
20 2 110,041.9 238,262 37,942 121
244 136,095.9 296,335 44,614 148
242 4 137,345.0 296,052 44,975 148
243 143,702.9 318,429 46,484 196
242 3 145,126.6 317,462 47,730 196
FHT 26.5625 4 2 19,519.6 51,117 8,870 28
82 39,584.6 91,091 16,191 52
12 2 64,992.6 145,176 24,254 100
162 86,700.8 188,721 30,327 100
Table 5.  Resource Utilization for Packet Mode
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 19,053.9 46,418 7,955 28
10.3125 8 39,081.7 82,525 13,997 52
12 60,299.1 119,625 19,118 73
12.5 4 19,059.3 46,269 8,089 28
8 39,078.8 82,812 13,640 52
10 49,592.1 101,220 16,446 61
12 60,194.0 119,540 19,283 73
25.78125 4 19,384.1 46,904 8,511 28
6 30,743.2 69,717 11,903 52
8 39,597.7 83,422 14,726 52
10 54,807.8 117,479 18,491 100
12 64,799.1 133,987 21,708 100
PAM4 FGT 26.5625 4 18,941.2 50,892 9,122 28
42 19,188.2 50,779 9,123 28
8 38,323.8 90,313 16,707 52
82 38,962.0 90,559 16,363 52
12 63,295.2 144,816 24,128 100
122 63,646.1 144,472 24,065 100
16 83,734.9 187,686 31,257 100
162 85,016.2 187,420 31,078 100
20 108,441.1 239,821 37,327 121
202 110,069.7 238,487 37,438 121
24 4 134,998.7 298,308 44,999 148
24 2 4 137,074.0 296,602 45,167 148
243 142,631.2 318,727 46,647 196
24 2 3 144,778.5 318,315 46,519 196
28.125 20 109,253.0 239,918 38,022 121
20 2 110,152.3 237,645 38,776 121
244 136,024.2 295,922 44,271 148
242 4 137,271.7 295,691 45,088 148
243 143,640.5 318,925 45,995 196
242 3 144,933.4 317,863 47,114 196
FHT 26.5625 4 2 19,583.9 50,934 9,174 28
8 2 39,812.8 91,232 16,068 52
122 65,044.5 145,145 24,064 100
162 86,744.6 187,247 30,577 100
Table 6.  Resource Utilization for Interlaken Look-aside Mode
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 13,666.8 34,928 5,930 0
10.3125 8 27,944.1 59,472 10,591 0
12 43,764.5 86,303 15,579 0
12.5 4 13,686.3 35,004 5,952 0
8 27,956.5 59,628 10,534 0
10 35,276.9 74,320 12,929 0
12 43,748.9 86,233 15,538 0
25.78125 4 13,711.5 35,004 6,172 0
6 20,683.6 47,417 8,504 0
8 27,946.0 59,575 11,055 0
10 35,304.7 74,358 13,458 0
12 43,759.1 86,322 16,015 0
PAM4 FGT 26.5625 4 13,370.7 39,104 6,890 0
4 2 13,607.1 38,872 7,072 0
8 27,320.9 67,017 12,527 0
8 2 27,901.2 67,085 12,575 0
12 42,629.8 97,834 18,301 0
122 43,290.3 97,916 18,261 0
FHT 26.5625 42 13,989.5 39,289 6,749 0
8 2 28,659.2 67,615 12,337 0
12 2 44,525.9 97,874 18,638 0
2 With elastic FIFO buffer
3 User interface width = 32
4 User interface width = 24
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