Visible to Intel only — GUID: chb1614084291639
Ixiasoft
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals
5.2. F-Tile Interlaken IP Transmit User Interface Signals
5.3. F-Tile Interlaken IP Receive User Interface Signals
5.4. F-Tile Interlaken IP Management Interface Signals
5.5. F-Tile Interlaken IP Reconfiguration Interface Signals
5.6. F-Tile Interlaken Link and Miscellaneous Signals
Visible to Intel only — GUID: chb1614084291639
Ixiasoft
1.6. F-Tile Interlaken IP Release Information
The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Value | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
IP Version | 8.1.0 | |||||||||||
Quartus® Prime Version | 24.2 | |||||||||||
Release Date | 2024.07.02 | |||||||||||
Ordering Code and Product ID |
Note: The ordering code for Interlaken look-aside IP is same as the F-Tile Interlaken Intel FPGA IP.
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