F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

2.1.1. Intel® FPGA IP Evaluation Mode

The free Intel® FPGA IP Evaluation Mode allows you to evaluate licensed Intel® FPGA IP in simulation and hardware before purchase. Intel® FPGA IP Evaluation Mode supports the following evaluations without additional license:
  • Simulate the behavior of a licensed Intel® FPGA IP in your system.
  • Verify the functionality, size, and speed of the IP quickly and easily.
  • Generate time-limited device programming files for designs that include IPs.
  • Program a device with your IP and verify your design in hardware.

Intel® FPGA IP Evaluation Mode supports the following operation modes:

  • Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial JTAG cable connected between the JTAG port on your board and the host computer, which is running the Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Quartus® Prime software, and requires no Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IPs in the design support tethered mode, the evaluation time runs until any IP evaluation expires. If all of the IPs support unlimited evaluation time, the device does not time-out.
  • Untethered—Allows running the design containing the licensed IP for a limited time. The IP reverts to untethered mode if the device disconnects from the host computer running the Quartus® Prime software. The IP also reverts to untethered mode if any other licensed IP in the design does not support tethered mode.

When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IPs that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP for production, purchase a full production license for the IP.

You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.

Figure 3.  Intel® FPGA IP Evaluation Mode Flow
Note: Refer to each IP's user guide for parameterization steps and implementation details.

Altera licenses IPs on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IPs that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Intel® FPGA Self-Service Licensing Center.

The Intel® FPGA Software License Agreements govern the installation and use of licensed IPs, the Quartus® Prime design software, and all unlicensed IPs.

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