F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 7/08/2024
Public
Document Table of Contents

4.6. M20K ECC Support

If you turn on Enable M20K ECC support in your Interlaken IP variation, the IP takes advantage of the built-in device support for ECC checking in all M20K blocks configured in the IP on the device.

The feature performs single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP.

This feature enhances data reliability but increases latency and resource utilization. Without the ECC feature, a single M20K memory block can support a datapath width of 40 bits. With the ECC feature, eight of those bits are dedicated to the ECC, and an M20K memory block can support a maximum data path width of 32 bits. Therefore, when M20K ECC support is turned on the IP configures additional M20K memory blocks. The ECC check adds latency to the path through the memory block, and increases the amount of device memory used by your IP.