F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 7/08/2024
Public
Document Table of Contents

2.6. Compiling the Full Design and Programming the FPGA

Use the Start Compilation command on the Processing menu in the Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® device with the Programmer and verify the design in hardware. Quartus® Prime may give a critical warning if the HSSI parameters in the Quartus® Prime settings file (.qsf) to configure the FHT and FGT PMAs are not specified.

You can refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide (Configurable Intel® Quartus® Prime Software Settings) to configure the FHT and FGT PMAs using the Quartus® Prime software settings file. (.qsf)