F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks TX Transmit Buffer TX MAC TX PCS TX PMA 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

4.1.1.1. Transmit Path Blocks

The Interlaken IP core transmit data path has the following four main functional blocks:
  • TX Transmit Buffer
  • TX MAC
  • TX PCS
  • TX PMA

TX Transmit Buffer

The Interlaken IP core TX transmit buffer aligns the incoming user application data, itx_din_words in the IP core internal format.

TX MAC

The Interlaken IP core TX MAC performs the following functions:
  • Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet interleaving in the Interlaken protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.
  • Inserts calendar data in all burst and idle words, if you configure in-band flow control.
  • Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
  • Stripes and de-stripes between the user data (data width) and the number of lanes. Refer to Table 2: IP Core Theoretical Raw Aggregate Bandwidth in this document for more information on supported combinations.
  • Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width.

TX PCS

The FPGA soft logic implements TX PCS. In PAM4 mode, the IP core contain a soft logic transcoder block to work with RS FEC (544, 514) of the TX PMA. The Interlaken IP TX PCS block performs the following functions for each lane:
  • Inserts the meta frame words in the incoming data stream.
  • Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
  • Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
  • Performs 64B/67B encoding.
  • Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
  • Performs the Interlaken transcoding function to support the RS FEC (544, 514) of the TX PMA in PAM4 mode applications.

TX PMA

The Interlaken IP core TX PMA serializes the data and sends it out on the Interlaken link. TX PMA contains RS FEC block in PAM4 mode and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each FEC core block serves four streams, using the same system clock and resets. For further details on F-Tile FEC Core, refer to F-Tile Architecture and PMA/FEC Direct PHY IP User Guide.
Note: For a 10-lane configuration design, the F-Tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew. Therefore, resources of 12-lane configuration are consumed in a 10-lane configuration.
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