Visible to Intel only — GUID: mrx1614084263826
Ixiasoft
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals
5.2. F-Tile Interlaken IP Transmit User Interface Signals
5.3. F-Tile Interlaken IP Receive User Interface Signals
5.4. F-Tile Interlaken IP Management Interface Signals
5.5. F-Tile Interlaken IP Reconfiguration Interface Signals
5.6. F-Tile Interlaken Link and Miscellaneous Signals
Visible to Intel only — GUID: mrx1614084263826
Ixiasoft
1.1. F-Tile Interlaken IP Features
General features
- Compliant with the Interlaken Protocol Specification, Revision 1.2.
- Compliant with the Interlaken Reed-Solomon Forward Error Correction (RS-FEC) Extension Specification, Revision 1.1.
- Support for 1, 2, 3, 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 675 Gbps raw bandwidth. Refer to the IP Supported Combinations of Number of Lanes and Data Rates for more details on supported configurations.
- Support forper-lane data rates of 6.25, 10.3125, 12.5, 25.78125, 53.125, 56.25, and 106.25 Gbps using the Intel FPGA on-chip high-speed transceivers.
- All variants have support for the Interlaken look-aside feature.
User interface features
- Dynamically configurable BurstMax and BurstMin values.
- Packet mode and Interleaved mode for user data transfer.
- Up to 256 logical channels in out-of-the-box configuration.
- Multisegment user interface.
Flow-control features
- Optional out-of-band flow control blocks.
- Optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
- Error correction code (ECC) for memory block implementation with the IP.
Line-side features
- Per-lane data rate of 53.125 and 56.25 Gbps using pulse amplitude modulation (PAM4) FGT PMAs and 106.25 Gbps using the PAM4 FHT PMAs.
- Per lane data rates of 6.25, 10.3125, 12.5, 25.78125 Gbps using non-return-to-zero (NRZ) mode.
Number of Lanes | Lane Rate (Gbps) | ||||||
---|---|---|---|---|---|---|---|
6.25 | 10.3125 | 12.5 | 25.78125 | 53.125 | 56.25 | 106.25 | |
1 | - | - | - | - | - | - | Yes |
2 | - | - | - | - | Yes | - | Yes |
3 | - | - | - | - | - | - | Yes |
4 | Yes | - | Yes | Yes | Yes | - | Yes |
6 | - | - | - | Yes | Yes | - | - |
8 | - | Yes | Yes | Yes | Yes | - | - |
101 | - | - | Yes | Yes | Yes | Yes | - |
12 | - | Yes | Yes | Yes | Yes | Yes | - |
PMA Type | Lane Rate (Gbps) | Number of Lanes | User Interface Width (words) | Data Width (bits) | Raw Aggregate Bandwidth (Gbps) |
---|---|---|---|---|---|
FGT | 6.25 | 4 | 4 | 256 | 25 |
10.3125 | 8 | 8 | 512 | 82.5 | |
12 | 8 | 512 | 123.75 | ||
12.5 | 4 | 4 | 256 | 50 | |
8 | 8 | 512 | 100 | ||
10 | 8 | 512 | 125 | ||
12 | 8 | 512 | 150 | ||
25.78125 | 4 | 4 | 256 | 103.125 | |
6 | 8 | 512 | 154.6875 | ||
8 | 8 | 512 | 206.25 | ||
10 | 16 | 1024 | 257.8125 | ||
12 | 16 | 1024 | 309.375 | ||
53.125 | 2 | 4 | 256 | 106.25 | |
4 | 8 | 512 | 212.5 | ||
6 | 16 | 1024 | 318.75 | ||
8 | 16 | 1024 | 425 | ||
10 | 16 | 1024 | 531.25 | ||
12 | 32 | 2048 | 637.5 | ||
56.25 | 10 | 16 | 1024 | 562.5 | |
12 | 32 | 2048 | 675 | ||
FHT | 106.25 | 1 | 4 | 256 | 106.25 |
2 | 8 | 512 | 212.5 | ||
3 | 16 | 1024 | 318.75 | ||
4 | 16 | 1024 | 425 |
1 For a 10-lane configuration design, the F-Tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew.