Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10
Visible to Intel only — GUID: tln1470780544314
Ixiasoft
Visible to Intel only — GUID: tln1470780544314
Ixiasoft
1.3. Resource Utilization
Resource utilization changes depending on the parameter settings you specify in the Stratix® 10 LL 40GbE parameter editor. For example, if you turn on statistics counters in the Stratix® 10 LL 40GbE parameter editor, the IP core requires additional resources to implement the additional functionality.
IP Core Variation | A | B | C | E | F |
---|---|---|---|---|---|
Parameter | |||||
Ready latency | 0 | 0 | 3 | 3 | 3 |
Use external TX MAC PLL | On | On | — | — | — |
Enable TX CRC insertion | — | On | On | On | On |
Enable link fault generation | — | — | On | — | — |
Enable preamble passthrough | — | — | On | — | — |
Enable MAC stats counters | — | On | On | On | On |
Enable KR4/CR4 | — | — | — | On | On |
Include FEC sublayer | — | — | — | — | On |
IP Core Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
---|---|---|---|
A | 7900 | 19100 | 1 |
B | 11200 | 25500 | 1 |
C | 12400 | 26900 | 1 |
E | 17000 | 32800 | 11 |
F | 17000 | 33200 | 11 |