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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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1.3. Resource Utilization
Resource utilization changes depending on the parameter settings you specify in the Stratix® 10 LL 40GbE parameter editor. For example, if you turn on statistics counters in the Stratix® 10 LL 40GbE parameter editor, the IP core requires additional resources to implement the additional functionality.
IP Core Variation | A | B | C | E | F |
---|---|---|---|---|---|
Parameter | |||||
Ready latency | 0 | 0 | 3 | 3 | 3 |
Use external TX MAC PLL | On | On | — | — | — |
Enable TX CRC insertion | — | On | On | On | On |
Enable link fault generation | — | — | On | — | — |
Enable preamble passthrough | — | — | On | — | — |
Enable MAC stats counters | — | On | On | On | On |
Enable KR4/CR4 | — | — | — | On | On |
Include FEC sublayer | — | — | — | — | On |
IP Core Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
---|---|---|---|
A | 7900 | 19100 | 1 |
B | 11200 | 25500 | 1 |
C | 12400 | 26900 | 1 |
E | 17000 | 32800 | 11 |
F | 17000 | 33200 | 11 |
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