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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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6.3. Transceivers Signals
The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. For Stratix® 10 LL 40GbE IP core, you can use the same ATX PLL for all four transceivers. In many cases, the same ATX PLL can serve as input to additional transceivers that have similar input clocking requirements. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
Signal |
Direction |
Description |
---|---|---|
tx_serial[3:0] | Output | TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair. |
rx_serial[3:0] | Input | RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair. |
clk_ref | Input | The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz . |
tx_serial_clk | Input | High speed serial clock driven by the ATX PLL. The frequency of this clock is 5.15625 GHz. The IP core fans out the clock to target each of the four transceiver PHY links. You must drive this clock from a single TX transceiver PLL that you configure separately from the Stratix® 10 LL 40GbE IP core. |
tx_pll_locked | Input | Lock signal from ATX PLL. Indicates the ATX PLL is locked. |