Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

ID 683600
Date 5/31/2024
Public
Document Table of Contents

6.3. Transceivers Signals

The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. For Stratix® 10 LL 40GbE IP core, you can use the same ATX PLL for all four transceivers. In many cases, the same ATX PLL can serve as input to additional transceivers that have similar input clocking requirements. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
Table 15.   Transceiver Signals

Signal

Direction

Description

tx_serial[3:0] Output TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[3:0] Input RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz .
tx_serial_clk Input High speed serial clock driven by the ATX PLL. The frequency of this clock is 5.15625 GHz.

The IP core fans out the clock to target each of the four transceiver PHY links. You must drive this clock from a single TX transceiver PLL that you configure separately from the Stratix® 10 LL 40GbE IP core.

tx_pll_locked Input Lock signal from ATX PLL. Indicates the ATX PLL is locked.