Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

ID 683600
Date 5/31/2024
Public
Document Table of Contents

11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device

The Stratix® 10 Low Latency 40G Ethernet targets an Stratix® 10 device. However, it is not a straightforward Stratix® 10 device targeted port of the Low Latency 40GbE IP core that targets an Arria® 10 device. The signals, registers, and register fields are different: you cannot simply substitute the Stratix® 10 IP core for the Arria® 10 or Stratix® V IP core in your design without additional design work.

Table 31.  Major Differences Between the Stratix® 10 Low Latency 40G Ethernet IP Core and the Low Latency 40G Ethernet IP Core
The comparison is defined relative to these versions:
  • Stratix® 10 Low Latency 40G Ethernet IP core available with the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
  • Low Latency 40GbE IP core for Arria® 10 devices, available with the Quartus® Prime software release v17.0.
This table does not list individual signal name and register differences.

Property

Stratix® 10 Low Latency 40G Ethernet IP Core

Low Latency 40G Ethernet IP Core For Arria 10 Device

Device support

Supports Stratix® 10 device family.

Supports Arria® 10 device family.

Reset

Provides three asynchronous hard reset signals (general, RX-only, and TX-only) and three soft reset register bits.

Supports single asynchronous hard reset signal and three soft reset register bits.

Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 256-bit data bus or custom streaming interface 128-bit data bus.

Avalon® streaming TX client interface readyLatency Avalon® streaming TX interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming TX interface readyLatency is always 0.
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on the TX client interface bus (l4_tx_data or din), and the IP core provides the preamble on the RX client interface bus (l4_rx_data or dout_d).
Interface to transceiver TX PLL You must instantiate a single TX PLL IP core to connect to the single tx_serial_clk input pin of the Stratix® 10 LL 40GbE IP core. You can instantiate one to four TX PLL IP cores to connect to the four distinct tx_serial_clk input pins of the LL 40GbE IP core.
Statistics counters Available as a configuration option (parameter). RX and TX statistics counters available independently as two distinct configuration options (parameters).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. Individual tx_inc_ and rx_inc_ signals available per possible statistics registers, whether or not statistics registers are enabled.
40GBASE-KR4 Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012. 40GBASE-KR4 available as a configuration option. Implements the IEEE Backplane Ethernet Standard 802.3ap-2007.
Flow control Not yet available in this release. Available as a configuration option (parameter).
1588 PTP support Not supported. N/A
Enable alignment of EOP on FCS word Always turned on. Available as a configuration option (parameter).
Minimum average interpacket gap Value is 12 bytes. Values none (single byte), 8 bytes, and 12 bytes available as configuration options (parameter).