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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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4.1.2.1. IP Core Preamble Processing
If you turn on Enable preamble passthrough in the parameter editor, the RX MAC forwards preamble bytes. The TX MAC requires the preamble bytes to be included in the frames at the Avalon® Streaming interface.
If you turn off Enable preamble passthrough, the IP core removes the preamble bytes. l2_rx_startofpacket is aligned to the MSB of the destination address.
Note that a single parameter in the Stratix® 10 LL 40GbE parameter editor turns on both RX and TX preamble passthrough.