Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

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ID 683600
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Core 2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device 12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
1. About the Low Latency 40G Ethernet Core x
1.1. Stratix® 10 LL 40GbE IP Core Supported Features 1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Stratix® 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Stratix® 10 Low Latency 40G Ethernet Core
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Stratix® 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Stratix® 10 LL 40GbE Core Functional Description x
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath 4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide

12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide

Date Quartus® Prime Version IP version Changes
2024.05.31 21.3 19.1.0
  • Updated instructions for ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition in Table: IP Core Generated Files.
  • Updated document title to Low Latency 40G Ethernet Intel® FPGA IP User Guide: Stratix® 10.
  • Renamed Datasheet to About the Low Latency 40G Ethernet Core section.
2023.06.20 21.3 19.1.0 Removed 0x340 register from Table: PHY Registers.
2021.10.12 21.3 19.1.0 Changed the device support level for the Stratix® 10 devices to Final.
2021.03.08 20.3 19.1.0 Removed the .sip file type from section: Generated File Structure.
2020.10.05 20.3 19.1.0
  • Corrected the width of the reconfiguration address from reconfig_address[10:0] to reconfig_address[12:0].
  • Removed outdated Use debug CPU parameter from the Stratix® 10 LL 40GbE IP Core Parameters: 40GBASE-KR4/CR4 Tab table.
  • Revised the Flow Control Signals table to update the following signals description:
    • pause_insert_tx0[(FCQN-1):0]
    • pause_insert_tx1[(FCQN-1):0]
    • pause_insert_rx[(FCQN-1):0]
  • Added new section: Ethernet Toolkit Overview.
2020.06.22 20.2 19.1.0
  • Updated the Stratix® 10 LL 40GbE IP Core Parameters: Main Tab table to include the following parameters:
    • Enable MAC flow control
    • Number of queues in priority flow control
    • Enable JTAG to Avalon Master Bridge
  • Updated the Stratix® 10 LL 40GbE Signals and Interfaces figure:
    • Added missing flow control signals
    • Removed undirectional support and link fault signals.
  • Added new section: Flow Control Interface.
  • Removed undirectional_en and link_fault_gen_en signals from the Avalon® Memory-Mapped Interface Interface table.
  • Added EIO_RX_SOFT_PURGE_S register description in the PHY Registers table.
  • Revised clk_status frequency range in the Avalon® Memory-Mapped Management Interface table. The frequency of this clock is 100-161 MHz.
2019.12.13 19.3 19.1.0
  • Added note clarifying auto adaptation support in the Transceiver Reconfiguration Signals section.
  • Rebranded Qsys to Platform Designer (Standard).
2019.09.30 19.3 19.1.0
  • Replaced Altera Debug Master Endpoint (ADME) with Native PHY Debug Master Endpoint (NPDME).
  • Removed note from Auto-Negotiation Master parameter in the Stratix® 10 LL 40 GbE IP Core Parameters: 40GBASE-KR4/CR4 Tab table.
  • Added Stratix® 10 Low Latency 40G Ethernet FPGA IP Core User Guide Archives.
  • Added Ethernet Link Inspector support in the Debugging the Link section.
  • Remove mention of 1588 PTP support in the Major Differences Between the Stratix® 10 LL 40GbE IP Core and the Low Latency 40GbE IP Core table.
Date Version Changes
2017.05.08 Quartus Prime Pro 17.1 Stratix 10 ES Editions
2016.09.09 Quartus Prime Pro-Stratix 10 Edition Beta Initial release.
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