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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme. If an IP core version is not listed, the user guide for the previous IP core version applies.
Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
20.3 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
20.2 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
19.3 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
17.1 S10 ES | 17.1 S10 ES | Low Latency 40-Gbps Ethernet IP Core User Guide 17.1 S10 ES |