Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

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ID 683600
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Core 2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device 12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
1. About the Low Latency 40G Ethernet Core x
1.1. Stratix® 10 LL 40GbE IP Core Supported Features 1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Stratix® 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Stratix® 10 Low Latency 40G Ethernet Core
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Stratix® 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Stratix® 10 LL 40GbE Core Functional Description x
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath 4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide

1.1. Stratix® 10 LL 40GbE IP Core Supported Features

The Stratix® 10 LL 40GbE IP core supports the following features:

  • Parameterizable through the IP Catalog available with the Quartus® Prime Pro Edition software.
  • Designed to the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
  • Soft PCS logic that interfaces seamlessly to Intel® FPGA 10.3125 gigabits per second (Gbps) serial transceivers.
  • Standard XLAUI external interface consisting of FPGA hard serial transceiver lanes operating at 10.3125 Gbps.
  • Supports 40GBASE-KR4/CR4 PHY and forward error correction (FEC) option for interfacing to backplanes. The option implements the IEEE Backplane Ethernet Standard 802.3-2012.
    • Supports option for auto-negotiation per Clause 73.
    • Supports option for link training per Clause 72.
    • Supports option for KR-FEC per Clause 74.
    • 40GBASE-KR4/CR4 PHY based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
  • Supports Synchronous Ethernet (SyncE) by providing an optional CDR recovered clock output signal to the device fabric.
  • Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • Avalon-ST data path interface connects to client logic with the start of frame in the most significant byte (MSB). Interface has data width 128 bits.
  • Support for jumbo packets, defined as packets greater than 1500 bytes.
  • Receive (RX) CRC removal and pass-through control.
  • Optional transmit (TX) CRC generation and insertion.
  • RX CRC checking and error reporting.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • Optional RX strict SFD checking per IEEE specification.
  • RX malformed packet checking per IEEE specification.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Received control frame type indication.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard
  • Hardware and software reset control.
  • MAC provides RX cut-through frame processing, no RX store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Optional access to Native PHY Debug Master Endpoint (NPDME) for serial link debugging.
  • Programmable ready latency of 0 or 3 clock cycles for Avalon-ST TX interface.
  • Optional statistics counters.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.

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