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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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6.5. Avalon® Memory-Mapped Management Interface
You access control and status registers using an Avalon® memory-mapped management interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the csr_rst_n signal. Asserting the csr_rst_n signal resets all control and status registers except the statistics registers; while this reset is in process, the Avalon® memory-mapped management interface does not respond.
Signal |
Direction |
Description |
---|---|---|
clk_status | Input | The clock that drives the control and status registers. The frequency of this clock is 100-161 MHz. |
reset_status | Input | Connect this signal to 1'b0. This signal remains visible as a top-level signal for backward compatibility. |
status_addr[15:0] | Input | Drives the Avalon® memory-mapped register address. |
status_read | Input | When asserted, specifies a read request. |
status_write | Input | When asserted, specifies a write request. |
status_readdata[31:0] | Output | Drives read data. Valid when status_readdata_valid is asserted. |
status_readdata_valid | Output | When asserted, indicates that status_read_data[31:0] is valid. |
status_writedata[31:0] | Input | Drives the write data. The packet can end at any byte position. The empty bytes are the low-order bytes. |
status_waitrequest | Output | Indicates that the control and status interface is not ready to complete the transaction. status_waitrequest is only used for read transactions. |
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