Visible to Intel only — GUID: fhy1471368636733
Ixiasoft
Visible to Intel only — GUID: fhy1471368636733
Ixiasoft
6.1. TX MAC Interface to User Logic
Signal |
Direction |
Description |
---|---|---|
clk_txmac | Output | The TX clock for the IP core is clk_txmac. The frequency of this clock is 312.5 MHz. If you turn on Use external TX MAC PLL in the Stratix® 10 LL 40GbE parameter editor, the clk_txmac_in input clock drives clk_txmac. |
l2_tx_data[127:0] | Input | Data input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. |
l2_tx_preamble[63:0] | Input | User preamble data. Available when you turn on Enable preamble passthrough in the Stratix® 10 LL 40GbE parameter editor. User logic drives the custom preamble data when l2_tx_startofpacket is asserted. |
l2_tx_valid | Input | When asserted, indicates valid data. |
l2_tx_startofpacket | Input | When asserted, indicates the first byte of a frame. When l2_tx_startofpacket is asserted, the MSB of l2_tx_data drives the start of packet. Packets that drive l2_tx_startofpacket and l2_tx_endofpacket in the same cycle are ignored. |
l2_tx_endofpacket | Input | When asserted, indicates the end of a packet. Packets that drive l2_tx_startofpacket and l2_tx_endofpacket in the same cycle are ignored. |
l2_tx_empty[3:0] | Input | Specifies the number of empty bytes when l2_tx_endofpacket is asserted. |
l2_tx_ready | Output | When asserted, indicates that the MAC can accept the data. The IP core asserts the l2_tx_ready signal on clock cycle <n> to indicate that clock cycle <n + readyLatency> is a ready cycle. The client may only assert l2_tx_valid and transfer data during ready cycles. |
l2_tx_error | Input | When asserted in an EOP cycle (while l2_tx_endofpacket is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.
Note: This functionality is not available in the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
|
l2_txstatus_valid | Output | When asserted, indicates that l2_txstatus_data and l2_txstatus_error[6:0] are driving valid data. |
l2_txstatus_data[39:0] | Output | Specifies information about the transmit frame. The following fields are defined:
|
l2_txstatus_error[6:0] | Output | Specifies the error type in the transmit frame. The following fields are defined:
|