Visible to Intel only — GUID: yap1471407484979
Ixiasoft
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
Visible to Intel only — GUID: yap1471407484979
Ixiasoft
6.6. Miscellaneous Status and Debug Signals
The miscellaneous status and debug signals are asynchronous.
Signal |
Direction |
Description |
---|---|---|
tx_lanes_stable | Output | Asserted when all TX lanes are stable and ready to transmit data. |
rx_block_lock | Output | Asserted when all lanes have identified 66-bit block boundaries in the serial data stream. |
rx_am_lock | Output | Asserted when all lanes have identified alignment markers in the data stream. |
rx_pcs_ready | Output | Asserted when the RX lanes are fully aligned and ready to receive data. |
local_fault_status | Output | Asserted when the RX MAC detects a local fault. This signal is available only if you turn on Enable link fault generation in the parameter editor. |
remote_fault_status | Output | Asserted when the RX MAC detects a remote fault. This signal is available only if you turn on Enable link fault generation in the parameter editor. |