Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

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ID 683600
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Core 2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device 12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
1. About the Low Latency 40G Ethernet Core x
1.1. Stratix® 10 LL 40GbE IP Core Supported Features 1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Stratix® 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Stratix® 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Stratix® 10 Low Latency 40G Ethernet Core
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Stratix® 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Stratix® 10 LL 40GbE Core Functional Description x
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath 4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Stratix® 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Stratix® 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide

2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters

The Low Latency 40G Ethernet parameter editor has an IP tab with two subtabs, the Main tab and the 40GBASE-KR4/CR4 tab.

The Low Latency 40G Ethernet parameter editor also includes an Example Design tab. For information about that tab, refer to the Stratix® 10 Low Latency 40G Ethernet Design Example User Guide .

Table 7.   Low Latency 40G Ethernet IP Core Parameters: Main Tab
Parameter Range Default Setting Description
General
Target transceiver tile

H-Tile, L-tile

The tile type of the Quartus® Prime project specific target device. Specifies the transceiver tile on your target device. The Device setting of the Quartus® Prime project in which you generate the IP core determines the transceiver tile type.

Unfortunately, at the time of publication (2017.05.08), the parameter editor displays a grayed-out listing of H-Tile in all cases. You can ignore this display; the IP core you generate does in fact target the correct transceiver tile type for your target Stratix® 10 device.

Protocol speed 40GbE 40GbE Selects the Ethernet data rate.
Ready latency 0, 3 0 Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l2_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the TX datapath.

PCS/PMA Options
Use external TX MAC PLL Enabled, Disabled Disabled When enabled, the IP core is configured to expect an input clock to drive the TX MAC. The input clock signal is clk_txmac_in.
Enable SyncE Enabled, Disabled Disabled Exposes the RX recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.8261, G.8262, and G.8264 recommendations.
PHY reference frequency

322.265625 MHz, 644.53125 MHz

644.53125 MHz

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100ppm).
VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1_0V, 1_1V 1_0V

Specifies whether the transceiver supply voltage is 1.0 V or 1.1 V. The supply voltage must match the voltage you specify for this parameter.

MAC Options
Enable TX CRC insertion Enabled, Disabled Enabled When enabled, TX MAC computes and inserts the CRC-32 checksum in the out-going Ethernet frame. When disabled, the TX MAC does not compute a 32-bit FCS in the TX MAC frame. Instead, the client must provide frames with at least 64 bytes, plus the Frame Check Sequence (FCS).
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Ethernet Standard. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled, Disabled Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic. The statistics module also supports shadow requests that verify counts by taking snapshots of intermediate results.
Enable Strict SFD check Enabled, Disabled Disabled When enabled, the IP core can implement strict SFD checking, depending on register settings.
Flow Control Options
Enable MAC flow control Enabled, Disabled Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames.
Number of queues in priority flow control 1-8 8 Specifies the number of queues used in managing flow control.
Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint (NPDME) Enabled, Disabled Disabled
If enabled, the IP core turns on the following features in the Native PHY IP core that is included in the Stratix® 10 LL 40GbE IP core:
  • Enable Native PHY Debug Master Endpoint (NPDME)
  • Enable capability registers

If turned off, the IP core is configured without these features.

For information about these Stratix® 10 features, refer to the Stratix® 10 L- and H-Tile Transceiver PHY User Guide.

Enable JTAG to Avalon Master Bridge Enabled, Disabled Disabled

If turned on, the IP core includes a JTAG to Avalon® memory-mapped interface master bridge connecting internally to status and reconfiguration registers.

This allows you to run the Ethernet Link Inspector using the System Console.

Table 8.   Stratix® 10 Low Latency 40G Ethernet IP Core Parameters: 40GBASE-KR4/CR4 Tab

Parameter

Range

Default Setting

Description

KR4/CR4 General Options

Enable KR4/CR4

  • True
  • False
 False

If this parameter is turned on, the IP core is a 40GBASE-KR4/CR4 variation. If this parameter is turned off, the IP core is not a 40GBASE-KR4/CR4 variation, and the other parameters on this tab are not available.

Note: At the time of publication (2017.05.08), the Quartus Prime Pro 17.1 Stratix 10 ES Editions software does not provide hardware support for 40GBASE-KR4/CR4 variations of this IP core. The SRAM Object File (.sof) you generate for these variations does not function correctly in hardware. However, you can generate, simulate, and compile these variations.
Status clock rate 100.0–161.0 MHz 100.0 MHz Sets the expected incoming clk_status frequency. The input clock frequency must match the frequency you specify for this parameter.

The IP core is configured with this information:

  • To ensure the IP core measures the link fail inhibit time accurately. Determines the value of the Link Fail Inhibit timer (IEEE 802.3 clause 73.10.2) correctly.
  • If clk_status frequency is not 100 MHz, to adjust the PHY clock monitors to report accurate frequency information.

This parameter determines the PHY Management clock (MGMT_CLK) frequency in MHz parameter of the underlying 10GBASE-KR PHY IP core. However, the default value of the Status clock rate parameter is not identical to the default value of the PHY IP core PHY Management clock (MGMT_CLK) frequency in MHz parameter.

Auto-Negotiation

Enable Auto-Negotiation

  • True
  • False

False

If this parameter is turned on, the IP core includes logic to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3–2012. If this parameter is turned off, the IP core does not include auto-negotiation logic and cannot perform auto-negotiation.

Currently the IP core can only negotiate to KR4 mode.

Link fail inhibit time for 40Gb Ethernet

500–510 ms

504 ms

Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto-Negotiation for Backplane Ethernet in IEEE Standard 802.3–2012.

The 40GBASE-KR4 IP core asserts the rx_pcs_ready signal to indicate link status is OK.

Enable 40GBASE-CR4 Technology Ability
  • True
  • False
 False If this parameter is turned on, the IP core advertises CR-4 capability. If this parameter is turned off, but auto-negotiation is turned on, the IP core advertises KR-4 capability.

Auto-Negotiation Master

  • Lane 0
  • Lane 1
  • Lane 2
  • Lane 3

Lane 0

Selects the master channel for auto-negotiation.

Pause ability–C0

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Pause ability–C1

  • True
  • False

True

If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2008.

Link Training: General

Enable Link Training

  • True
  • False

True

If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3–2012.

Maximum bit error count

2n – 1 for n an integer in the range 4–10. 511

Specifies the maximum number of errors on a lane before the Link Training Error bit (40GBASE-KR4 register offset 0xD2, bit 4, 12, 20, or 28, depending on the lane) is set, indicating an unacceptable bit error rate.

n is the width of the Bit Error Counter that is configured in the IP core. The value to which you set this parameter determines n, and thus the width of the Bit Error Counter. Because the default value of this parameter is 511, the default width of the Bit Error Counter is 10 bits.

You can use this parameter to tune PMA settings. For example, if you see no difference in error rates between two different sets of PMA settings, you can increase the width of the bit error counter to determine if a larger counter enables you to distinguish between PMA settings.

Number of frames to send before sending actual data

  • 127
  • 255
127

Specifies the number of additional training frames the local link partner delivers to ensure that the link partner can correctly detect the local receiver state. This number is the value of wait_timer as specified in Clause 72.6.10.3.2 of IEEE Std 802.3–2012

Link Training: PMA Parameters

VMAXRULE

0–31 30

Specifies the maximum VOD.

VMINRULE

0–31 6

Specifies the minimum VOD.

VODMINRULE

0–31 14

Specifies the minimum VOD for the first tap.

VPOSTRULE

0–25 25

Specifies the maximum value that the internal algorithm for pre-emphasis ever tests in determining the optimum post-tap setting.

VPRERULE

0–16 16

Specifies the maximum value that the internal algorithm for pre-emphasis ever tests in determining the optimum pre-tap setting.

PREMAINVAL

0–31 30

Specifies the Preset VOD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3–2012.

Note: The default value is subject to change in future software releases.

PREPOSTVAL

0–31 0

Specifies the preset Post-tap value.

PREPREVAL

0–15 0

Specifies the preset Pre-tap value.

INITMAINVAL

0–31 25

Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3–2012.

Note: The default value is subject to change in future software releases.

INITPOSTVAL

0–25 13

Specifies the initial and reset Post-tap value.

Note: The default value is subject to change in future software releases.

INITPREVAL

0–16 3

Specifies the initial and reset Pre-tap value.

Note: The default value is subject to change in future software releases.

FEC Options

Include FEC sublayer

  • True
  • False

False

If this parameter is turned on, the IP core includes logic to implement FEC.

Set FEC_Ability bit on power up or reset

  • True
  • False

False

 If this parameter is turned on, the IP core sets the FEC ability bit (40GBASE-KR4 register offset 0xB0, bit 16: Assert KR FEC enable) on power up and reset.

This parameter is available if you turn on Include FEC sublayer.

Set FEC_Enable bit on power up or reset

  • True
  • False

False

 If this parameter is turned on, the IP core sets the FEC enable bit (40GBASE-KR4 register offset 0xB0, bit 18: Assert KR FEC request) on power up and reset. If you turn on this parameter but do not turn on Set FEC_ability bit on power up or reset, this parameter has no effect: the IP core cannot specify the value of 1 for FEC Requested without specifying the value of 1 for FEC Ability.

This parameter is available if you turn on Include FEC sublayer.

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