Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

ID 683600
Date 5/31/2024
Public
Document Table of Contents

1.3. Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the Stratix® 10 LL 40GbE parameter editor. For example, if you turn on statistics counters in the Stratix® 10 LL 40GbE parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 4.  IP Core Variation Encoding for Resource Utilization TableIP core variations are named for easy comparison with the Arria 10 Low Latency 40GbE IP core. "On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C E F
Parameter
Ready latency 0 0 3 3 3
Use external TX MAC PLL On On
Enable TX CRC insertion On On On On
Enable link fault generation On
Enable preamble passthrough On
Enable MAC stats counters On On On On
Enable KR4/CR4 On On
Include FEC sublayer On
Table 5.  IP Core FPGA Resource UtilizationLists the resources and expected performance for selected variations of the Stratix® 10 LL 40GbE IP core in a Stratix 10 device.

These results were obtained using the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

Memory

M20K

A 7900 19100 1
B 11200 25500 1
C 12400 26900 1
E 17000 32800 11
F 17000 33200 11