Visible to Intel only — GUID: glg1471368655017
Ixiasoft
Visible to Intel only — GUID: glg1471368655017
Ixiasoft
6.2. RX MAC Interface to User Logic
Signal |
Direction |
Description |
---|---|---|
clk_rxmac | Output | Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 312.5 MHz. All RX MAC interface signals are synchronous to clk_rxmac. |
l2_rx_data[127:0] | Output | Data output from the MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard. |
l2_rx_preamble[63:0] | Output | Received preamble data. Available when you select PREAMBLE PASS-THROUGH mode. Valid when l2_rx_startofpacket is asserted. |
l2_rx_valid | Output | When asserted, indicates that l2_rx_data[127:0] is driving data. |
l2_rx_startofpacket | Output | When asserted, indicates the first byte of a frame. |
l2_rx_endofpacket | Output | When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position. |
l2_rx_empty[3:0] | Output | Specifies the number of empty bytes when l2_rx_endofpacket is asserted. The packet can end at any byte position. The empty bytes are the low-order bytes. |
l2_rx_error[5:0] | Output | When asserted in the same cycle as l2_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l<n>_rx_error specify the following errors:
|
l2_rxstatus_valid | Output | When asserted, indicates that l2_rxstatus_data is driving valid data. |
l2_rxstatus_data[39:0] | Output | Specifies information about the received frame. The following fields are defined:
|