Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

ID 683600
Date 5/31/2024
Public
Document Table of Contents

3.5.2. Adding the Transceiver PLL

Stratix® 10 Low Latency 40G Ethernet IP cores require an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.

Figure 4. PLL Configuration ExampleThe TX transceiver PLL is instantiated with an Intel® FPGA ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the Stratix® 10 Low Latency 40G Ethernet IP core.

You can use the IP Catalog to create a transceiver PLL.

  • Select Stratix 10 Transceiver ATX PLL.
  • In the parameter editor, set the following parameter values:
    • PLL output frequency to 5156.25 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 Gbps data rate through the transceiver.
    • PLL integer reference clock frequency to 644.53125 MHz.

You must connect the tx_serial_clk input pin of the Stratix® 10 Low Latency 40G Ethernet IP core PHY link to the output port of the ATX PLL.