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Ixiasoft
Visible to Intel only — GUID: thp1479167108381
Ixiasoft
1. Overview
Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications.
The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the hardened IP blocks for PCI Express* and Ethernet applications.
The Intel® Stratix® 10 device introduces several transceiver tile variants to support a wide variety of protocol implementations. These transceiver tile variants are L-tiles, H-tiles, and E-tiles. This user guide describes both the L- and H-tile transceivers. For Intel® Stratix® 10 devices that only contain E-tiles, refer to the E-Tile Transceiver PHY User Guide.
Feature | L-Tile | H-Tile | E-Tile |
---|---|---|---|
Maximum Transceiver Data Rate (Chip-to-chip) | GX 1—17.4 Gbps GXT 1—26.6 Gbps |
GX—17.4 Gbps GXT—28.3 Gbps |
GXE 2—57.8 Gbps Pulse Amplitude Modulation 4 (PAM4)/28.9 Gbps Non-return to zero (NRZ) |
Maximum Transceiver Data Rate (Backplane) | GX—12.5 Gbps GXT—12.5 Gbps |
||
Number of Transceiver Channels (per tile) | GX—16 per tile GXT—8 per tile Total—24 per tile (4 banks, 6 channels per bank) |
GX—8 per tile GXT—16 per tile Total—24 per tile (4 banks, 6 channels per bank) |
GXE—24 individual channels per tile |
Hard IP (per tile) | PCIe* —Gen3 x16 | PCIe* —Gen3 x16, SR-IOV (4 PF, 2K VF) Ethernet—100GbE MAC |
Ethernet—100GbE MAC and RS (528, 514)-FEC, 4 per tile Ethernet—KP-FEC, 4 per tile Ethernet—10/25GbE MAC and RS (528, 514)-FEC, 24 per tile |
In all Intel® Stratix® 10 devices, the various transceiver tiles connect to the FPGA fabric using Intel EMIB (Embedded Multi-Die Interconnect Bridge) technology.
Section Content
L-Tile/H-Tile Layout in Intel Stratix 10 Device Variants
L-Tile/H-Tile Counts in Intel Stratix 10 Devices and Package Variants
L-Tile/H-Tile Building Blocks
Overview Revision History