AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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3.3.13.4. Toolkit Explorer

For designs with debug-enabled IP, the Toolkit Explorer automatically lists the toolkits available for the IP in the design, including the transceiver toolkits.

You can access Toolkit Explorer in the GUI by selecting Tools > System Debugging Tools > System Debugging Toolkits or by going to the Toolkit Explorer pane in the System Console.

The following toolkits are available:
Table 30.  Toolkits Available in System Console Toolkit Explorer
Toolkit Description Toolkit Documentation
EMIF Calibration Debug Toolkit Helps you to debug external memory interfaces by accessing calibration data obtained during memory calibration. The analysis tools can evaluate the stability of the calibrated interface and assess hardware conditions.
  • External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide
EMIF Traffic Generator Configuration Toolkit

Helps you to debug external memory interfaces by sending sample traffic through the external memory interface to the memory device. The generated EMIF design example includes a traffic generator block with control and status registers.

EMIF Efficiency Monitor Toolkit Helps you to debug external memory interfaces by measuring efficiency on the Avalon interface in real time. The generated EMIF design example can include the Efficiency Monitor block.
  • External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide
Ethernet Toolkit Helps you to interact with and debug an Ethernet Intel FPGA IP interface in real time. You can verify the status of the Ethernet link, assert and deassert IP resets, verifies the IP error correction capability, Ethernet Toolkit User Guide
Intel® Stratix® 10 FPGA P-Tile Toolkit (for PCIe) Helps you to optimize the performance of large-size data transfers with real-time control, monitoring, and debugging of the PCI Express* links at the Physical, Data Link, and Transaction layers. Intel FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* User Guide
Serial Lite IV IP Toolkit An inspection tool that monitors the status of a Serial Lite IV IP link and provides a step-by-step guide for the IP link initialization sequences.
  • Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide
  • Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
Intel® Arria® 10 and Intel® Cyclone® 10 GX Transceiver Native PHY Toolkit Helps you to optimize high-speed serial links in your board design by providing real-time control, monitoring, and debugging of the transceiver links running on your board.  
L-Tile and H-Tile Transceiver Native PHY Toolkit
E-Tile Transceiver Native PHY Toolkit