AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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3.3.15.1. Hyper-Aware Design Flow

Use the Hyper-Aware design flow to shorten design cycles and optimize performance for designs targeting Intel® Agilex™ and Intel® Stratix® 10 devices. The Hyper-Aware design flow combines automated register retiming (Hyper-Retiming), with implementation of targeted timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for Intel® Agilex™ and Intel® Stratix® 10 designs.

Fast Forward Compilation operates on the post-retimed netlist and outputs Fast Forward Timing Closure Recommendations that show the current and potential performance achievable for each clock domain after applying Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization steps.