AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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3.3.7.1. Pin Planner

The Intel® Quartus® Prime Pro Edition Pin Planner provides a graphical package view, allowing you to validate I/O assignments by performing legality checks on a design's I/O pins and surrounding logic.
With the Pin Planner, you can identify I/O banks, VREF groups, and differential pin pairings to help you with the I/O planning process. To access the Pin Planner, click Assignments > Pin Planner.
Note: Modifications that you make in the Pin Planner affect the .qsf file.
Figure 7.  Intel® Quartus® Prime Pro Edition Pin PlannerTo invoke the Pin Planner, click Assignments > Pin Planner