AN 307: Intel® FPGA Design Flow for Xilinx* Users

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Date 2/25/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users 2. Technology Comparison 3. FPGA Tools Comparison 4. Xilinx* to Intel® FPGA Design Conversion 5. Conclusion 6. AN 307: Intel® FPGA Design Flow for Xilinx* Users Archives 7. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison x
2.1. Intel® FPGA and SoC Devices 2.2. Intel® - Xilinx* Device Comparison 2.3. Intel® FPGA Device Features
3. FPGA Tools Comparison x
3.1. Hardware and Software Tools for FPGA Design 3.2. FPGA Design Flow Using Command Line Scripting 3.3. FPGA Design Flow Using Tools with GUIs 3.4. Additional Intel® Quartus® Prime Pro Edition Features
3.2. FPGA Design Flow Using Command Line Scripting x
3.2.1. Command-Line Executable Equivalents 3.2.2. Programming and Configuration File Support in the Intel® Quartus® Prime Pro Edition Software
3.2.1. Command-Line Executable Equivalents x
3.2.1.1. synth_design 3.2.1.2. place_design/route_design 3.2.1.3. report_timing 3.2.1.4. write_bitstream 3.2.1.5. write_sdf/write_verilog/write_vhdl 3.2.1.6. report_power 3.2.1.7. write_checkpoint 3.2.1.8. Run Complete Design Flow
3.3. FPGA Design Flow Using Tools with GUIs x
3.3.1. Project Creation 3.3.2. Design Entry 3.3.3. IP Status 3.3.4. Design Constraints 3.3.5. Synthesis 3.3.6. Design Implementation 3.3.7. Finalize Pinout 3.3.8. Viewing and Editing Design Placement 3.3.9. Static Timing Analysis 3.3.10. Generation of Device Programming Files 3.3.11. Power Analysis 3.3.12. Simulation 3.3.13. Hardware Verification 3.3.14. View Netlist 3.3.15. Design Optimization 3.3.16. Techniques to Improve Productivity 3.3.17. Partial Reconfiguration 3.3.18. Cross-Probing in the Intel® Quartus® Prime Pro Edition Software
3.3.2. Design Entry x
3.3.2.1. HDL Editor 3.3.2.2. Schematic/Block Editor 3.3.2.3. State Machine Editor 3.3.2.4. IP Catalog and Parameter Editor 3.3.2.5. Platform Designer System Integration Tool 3.3.2.6. Platform Designer Component Editor
3.3.4. Design Constraints x
3.3.4.1. Assignment Editor 3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI 3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor
3.3.7. Finalize Pinout x
3.3.7.1. Pin Planner 3.3.7.2. Interface Planner 3.3.7.3. Tile Interface Planner
3.3.12. Simulation x
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
3.3.13. Hardware Verification x
3.3.13.1. System Console 3.3.13.2. Signal Tap Logic Analyzer 3.3.13.3. In-System Sources and Probes 3.3.13.4. Toolkit Explorer 3.3.13.5. Remote Debugging 3.3.13.6. Other Intel® FPGA Debugging Tools
3.3.13.4. Toolkit Explorer x
3.3.13.4.1. Transceiver Toolkit 3.3.13.4.2. EMIF Debug Toolkit
3.3.14. View Netlist x
3.3.14.1. RTL Viewer 3.3.14.2. Technology Map Viewer
3.3.15. Design Optimization x
3.3.15.1. Hyper-Aware Design Flow 3.3.15.2. Physical Synthesis Optimization 3.3.15.3. Optimization Modes 3.3.15.4. Fractal Synthesis
3.3.16. Techniques to Improve Productivity x
3.3.16.1. Fast Preservation 3.3.16.2. Engineering Change Order (ECO) Flow 3.3.16.3. Block-Based Design Flow 3.3.16.4. Design Assistant 3.3.16.5. Snapshot Viewer 3.3.16.6. Design Space Explorer II
3.4. Additional Intel® Quartus® Prime Pro Edition Features x
3.4.1. Scripting with Tcl in the Intel® Quartus® Prime Pro Edition Software
3.4.1. Scripting with Tcl in the Intel® Quartus® Prime Pro Edition Software x
3.4.1.1. Running Scripts from the DOS or UNIX Prompt 3.4.1.2. Running Scripts in Batch Mode from a Shell 3.4.1.3. Running Tcl Commands Directly from the Command Line 3.4.1.4. Running Tcl Commands Interactively from the Shell 3.4.1.5. The Intel® Quartus® Prime Tcl Console Window
4. Xilinx* to Intel® FPGA Design Conversion x
4.1. Replacing Xilinx* Primitives 4.2. Converting IP Cores 4.3. Setting Equivalent Xilinx* Design Constraints 4.4. Setting Up the Simulation Environment
4.1. Replacing Xilinx* Primitives x
4.1.1. Converting I/O Buffers 4.1.2. Changing Default I/O Standard for Pins 4.1.3. Converting Registers
4.1.1. Converting I/O Buffers x
4.1.1.1. Example of Converting I/O Buffer
4.2. Converting IP Cores x
4.2.1. Converting Memory Blocks 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) 4.2.3. Converting Multipliers
4.2.1. Converting Memory Blocks x
4.2.1.1. Embedded Memory Blocks 4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory 4.2.1.3. Determining Memory Block and Mapping Ports 4.2.1.4. Memory Port Mapping 4.2.1.5. Example: Converting Simple Dual-Port RAM
4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory x
4.2.1.2.1. Memory Mode 4.2.1.2.2. Clocking Mode 4.2.1.2.3. Write and Read Operation Triggering 4.2.1.2.4. Read-During-Write Operation at the Same Address 4.2.1.2.5. Error Correction Code (ECC) 4.2.1.2.6. Byte Enable 4.2.1.2.7. Address Clock Enable 4.2.1.2.8. Parity Bit Support 4.2.1.2.9. Memory Initialization 4.2.1.2.10. Output Synchronous Set/Reset
4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) x
4.2.2.1. Feature Comparison 4.2.2.2. Port Mapping Reference 4.2.2.3. Example: Converting Xilinx* MMCM into an Intel® PLL
4.2.3. Converting Multipliers x
4.2.3.1. Feature Comparison 4.2.3.2. Port Mapping 4.2.3.3. Example: Converting to the LPM_MULT IP Core 4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core
4.3. Setting Equivalent Xilinx* Design Constraints x
4.3.1. Device Constraints 4.3.2. Placement Constraints 4.3.3. Timing Constraints 4.3.4. Retimer Constraints
4.3.1. Device Constraints x
4.3.1.1. DRIVE 4.3.1.2. SLEW 4.3.1.3. IOB 4.3.1.4. IOSTANDARD 4.3.1.5. KEEP
4.3.2. Placement Constraints x
4.3.2.1. PBLOCK 4.3.2.2. PACKAGE_PIN 4.3.2.3. LOC & BEL 4.3.2.4. PROHIBIT
4.3.2.1. PBLOCK x
4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions
4.3.3. Timing Constraints x
4.3.3.1. Clock Domain Crossing
4.4. Setting Up the Simulation Environment x
4.4.1. Simulation Levels 4.4.2. HDL Support for EDA Simulators 4.4.3. Value Change Dump (VCD) Support 4.4.4. Simulating Intel FPGA IP Cores
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. AN 307: Intel® FPGA Design Flow for Xilinx* Users Archives
7. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users

4.2.1.5. Example: Converting Simple Dual-Port RAM

This example includes Verilog HDL and VHDL code for the top level that instantiates the Xilinx* simple dual-port RAM.

In this example, the top-level entity test instantiates sdp_ram, a Xilinx* simple dual-port RAM generated through Block Memory Generator, with the following properties:

Table 50.  Properties of Simple Dual-Port RAM
Input data width 16 bits
Memory depth 8 words
Clocking Mode Different input and output clocks
ECC feature Selected
Out data registered status Output registered (one stage pipeline)
Read-during-write WRITE_FIRST (New Data)

The original Verilog HDL Code in the Vivado* Software is: 

module test(
		input clka,
		input ena,
		input [0:0]wea,
		input [2:0]addra,
		input [15:0]dina,
		input clkb,
		input enb,
		input [2:0]addrb,
		output [1 5:0]doutb,
		output sbiterr,
		output dbiterr,
		output [2:0]rdaddrecc);
	simple dual port ip i1(
		.clka(clka),
		.ena(ena),
		.wea(wea),
		.addra(addra),
		.dina(dina),
		.clkb(clkb),
		.enb(enb),
		.addrb(addrb),
		.doutb(doutb),
		.sbiterr(sbiterr),
		.dbiterr(dbiterr),
		.rdaddrecc(rdaddrecc));
endmodule

The original VHDL Code in the Vivado* Software is: 

LIBRARY ieee;
USE ieee.STD_LOGIC 1164.all; LIBRARY work;
ENTITY test IS
	port (
		clka: IN STD_LOGIC;
		ena: IN STD_LOGIC;
		wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
		addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		clkb: IN STD_LOGIC;
		enb: IN STD_LOGIC;
		addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		dbiterr: OUT STD_LOGIC;
		sbiterr: OUT STD_LOGIC;
		rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END test;
ARCHITECTURE arch OF test IS
component simple dual port ip
	PORT(
		clka: IN STD_LOGIC;
		ena: IN STD_LOGIC;
		wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
		addra: IN STD_LOGIC VECTOR(2 DOWNTO 0);
		dina: IN STD_LOGIC VECTOR(15 DOWNTO 0);
		clkb: IN STD_LOGIC;
		enb: IN STD_LOGIC;
		addrb: IN STD_LOGIC VECTOR(2 DOWNTO 0);
		doutb: OUT STD_LOGIC VECTOR(15 DOWNTO 0);
		dbiterr: OUT STD_LOGIC;
		sbiterr: OUT STD_LOGIC;
		rdaddrecc: OUT STD_LOGIC vector ( 2 DOWNTO 0)
end component;
BEGIN
	il: simple_dual_port_ip
		PORT MAP(
			clka => clka,
			ena => ena,
			wea => wea,
			addra => addra,
			dina => dina,
			clkb => clkb,
			enb => enb,
			addrb => addrb,
			doutb => doutb,
			dbiterr => dbiterr,
			sbiterr => sbiterr,
			rdaddrecc => rdaddrecc);
END;

To convert a Xilinx* Simple Dual Port RAM to Intel® FPGA:

  1. Create an Intel® FPGA simple dual-port RAM through the Intel® Quartus® Prime software IP Catalog/Parameter Editor.
  2. Configure the RAM with the following options:
    Table 51.  Parameters of Simple Dual-Port RAM
    How will you be using the dual port RAM? Specifies how you use the dual port RAM.
      With one read port and one write port  
    Read/Write Ports Specifies the width of the input and output ports.
      How wide should the 'q_a' output bus be? 16 bits  
      How wide should the 'q_b' output bus be? 16 bits  
    What should the memory type be? Specifies the memory block type. The available memory blocks depend on the target device.
      RAM Block Type M20K  
    What clocking method do you want to use? Specifies the clocking method to use.
      Dual clock: use separate ‘read’ and ‘write’ clock A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers.
    ECC Checking  
      Enable Error Correction Check (ECC) On Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory
      Enable ECC Pipeline Registers On Specifies whether to enable the ECC pipeline registers before the output decoder to achieve that same performance as non-ECC mode at the expense of one cycle of latency
    Clock Enables Specifies whether to create clock enables for read and write registers.
      Use different clock enables for registers On  
      Use clock enable for write input registers On  
      Use clock enable for output registers On  
  3. Instantiate the new Intel® FPGA RAM. to replace the Xilinx* RAM.
    The converted Verilog HDL code in the Intel® Quartus® Prime Software after instantiating the new RAM: 
    module test(
	input clka,
	input ena,
	input [0:0]wea,
	input [2:0]addra,
	input [15:0]dina,
	input clkb,
	input enb,
	input [2:0]addrb,
	output [15:0]doutb,
	output sbiterr,
	output dbiterr,
	output [2:0]rdaddrecc);
simple_dual_port_ip i1(
			.wrclock (clka),
			.wrclocken (ena),
			.wren (wea),
			.wraddress (addra),
			.data (dina),
			.rdclock (clkb),
			.rdoutclocken (regceb | enb),
			.rdaddress (addrb),
			.q (doutb),
			.eccstatus ({dbiterr, sbiterr})
			);
			endmodule

    The converted VHDL code in the Intel® Quartus® Prime Software: 

    LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all; LIBRARY work;
ENTITY test IS
		port (
			clka: IN STD_LOGIC;
			ena: IN STD_LOGIC;
			wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
			addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
			clkb: IN STD_LOGIC;
			end: IN std_Iogic;
			addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			dbiterr: OUT STD_LOGIC;
			sbiterr: OUT STD_LOGIC;
			rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END test,
ARCHITECTURE arch OF test IS
component simple_dual_port_ip
	PORT(
		wrclock: IN STD_LOGIC;
		wrclocken: IN STD_LOGIC;
		wren: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
		wraddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		data: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		rdclock: IN STD_LOGIC;
		rdaddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		q: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
		eccstatus: OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
		);
end component;
signal eccstatus_o: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
	dbiterr <= eccstatus_o(1);
	sbiterr <= eccstatus_o(0);
	i1: simple_dual_port_ip
			PORT MAP(
				wrclock => clka,
				wrclocken => ena,
				wren => wea,
				wraddress => addra,
				data => dina,
				rdclock => clkb,
				rdaddress => addrb,
				q => doutb,
				eccstatus => eccstatus_o);
END;
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