AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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4.3.1.5. KEEP

Equivalent to the KEEP constraints, the Attribute Keep (VHDL) or Synthesis Keep (Verilog) synthesis attributes direct the Compiler to keep a wire or combinational node through logic synthesis minimizations and netlist optimizations. Similarly, you can also set the Implement as Output of Logic Cell logic option in the Intel® Quartus® Prime Assignment Editor.

The following example shows how both VHDL and Verilog HDL set the equivalent KEEP constraint (Differential SSTL-2 Class I) to the my_wire signal.

Verilog HDL example in the Vivado* software:

(* KEEP = "TRUE" *) wire my_wire

Equivalent Verilog HDL example in the Intel® Quartus® Prime software:

(	*preserve*) wire my_wire;

VHDL example in the Vivado* software:

signal my_wire: bit;
attribute keep: string;
attribute keep of my_wire: signal is "TRUE";

Equivalent VHDL example in the Intel® Quartus® Prime software:

signal my_wire: bit;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;