AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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4.3.3.1. Clock Domain Crossing

The following table shows how to convert Xilinx Vivado* XDC timing constraints for clock domain crossings to the equivalent Intel® Quartus® Prime Pro Edition Timing Analyzer SDC timing constraints.
Table 62.   Vivado* XDC versus Timing Analyzer SDC Timing Constraints for Clock Domain Crossing
Vivado XDC Timing Constraint Timing Analyzer SDC Command Description
set_clock_groups ‑asynchronous Removes the timing paths between two asynchronous clock domains.
set_bus_skew set_max_skew Constrains the skew within bits on a bus. This constraint ensures that related data arrives together.
set_max_delay ‑datapath_only set_data_delay Sets a maximum delay on a path, not including clock skew. This constraint ensures that data arrives in a reasonable amount of time.