AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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4.2.1.2.7. Address Clock Enable

Intel® FPGA memory supports the address clock enable feature. The address clock enable holds the previous address value for as long as addressstall is enabled. Xilinx* RAM blocks support an equivalent feature, called Address Enable.

For more information about the address clock enable feature, refer to the Embedded Memory Blocks chapter in your target device handbook.