AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.14.1. RTL Viewer

To run the RTL Viewer for an Intel® Quartus® Prime Pro Edition project:
  1. Click Processing > Start > Start Analysis & Elaboration to generate a RTL netlist
  2. To open the RTL Viewer, click Tools > Netlist Viewers (RTL Viewer).

Alternatively, you can perform a full compilation on any Intel® Quartus® Prime Pro Edition flow that includes the initial Analysis and Elaboration stage.