AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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3.3.14.2. Technology Map Viewer

The Technology Map Viewer is a detached window that provides a graphical representation of the schematic. To run the Technology Map Viewer for an Intel® Quartus® Prime Pro Edition project:

  1. Click Processing > Start > Start Analysis & Synthesis to synthesize and map the design to the target technology.
  2. Click Tools > Netlist Viewers > Technology Map Viewer (Post-Mapping) to view the post mapping netlist.
  3. Click Processing > Start > Start Fitter.

    After completing the Fitter stage, the Technology Map Viewer displays how the Fitter modified the netlist as a result of optimizations. After completing the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.

  4. Click Tools > Netlist Viewers > Technology Map Viewer (Post-Fitting) to view the post fitting netlist.

To find cells by name, click Edit > Find, type the cell name, and click List.