Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

6.2. Data Interface Signals

Table 12.  XGMII SignalsThe MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the MAC.
Signal Name Direction Clock Domain Description
xgmii_tx_dc[71:0] Input Synchronous to xgmii_tx_clk XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control. For interface mapping, refer to Table: TX XGMII Mapping to Standard SDR XGMII Interface.
xgmii_tx_clk Input Clock signal Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to xgmii_rx_clk. This clock can be connected to the tx_pma_div_clkout; however, Intel recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.

The frequencies are the same whether or not you enable FEC.

xgmii_rx_dc[71:0] Output Synchronous to xgmii_rx_clk RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control. For interface mapping, refer to Table: RX XGMII Mapping to Standard SDR XGMII Interface.
xgmii_rx_clk Input Clock signal Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_pma_div_clkout ; however, Intel recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.

The frequencies are the same whether or not you enable FEC.


Section Content
XGMII Mapping to Standard SDR XGMII Data

Level Two Title