Stratix® 10 10GBASE-KR PHY IP Core User Guide

Download PDF
ID 683500
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

4. Functional Description

The Intel FPGA 10GBASE-KR PHY IP core implements an Ethernet MAC in accordance with the 802.3 2015 Standard. The IP core implements an Ethernet PCS and PMA (PHY) that handles the frame encapsulation and flow of data between a client logic and Ethernet network. The following figure shows the supporting components inside the Stratix® 10 10GBASE-KR PHY IP core.

Figure 6.  Stratix® 10 10GBASE-KR PHY IP Core Block Diagram

The Stratix® 10 10GBASE-KR PHY IP core includes the following components:

Enhanced PCS Datapaths

The Enhanced PCS and PMA inside the Native PHY are configured as a 10GBASE-R PHY. Refer to the PCS architecture chapters of Stratix® 10 Transceiver PHY User Guide for more details on how these blocks support 10G protocols and FEC.

Auto Negotiation, IEEE 802.3 Clause 73

The auto-negotiation component synchronizes the start time of the link training on both sides of the link. This function ensures that the link training can complete in 500 ms or less, as required by the IEEE specification.

Link Training (LT), IEEE 802.3 Clause 72

Stratix® 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training procedure. This IP includes:

  • Training frame lock that is different from the regular 64b/66b frame_lock
  • Training frame generation
  • The control channel codec
  • Local Device (LD) coefficient update
  • Link Partner (LP) coefficient generation

Reconfiguration Block

The Reconfiguration Block performs Avalon® Memory-Mapped Interface ( Avalon® -MM) writes to the PHY for both PCS and PMA reconfiguration. The Avalon® -MM master accepts requests from the PMA or PCS controller. It performs Read-Modify-Write or Write commands on the Avalon® -MM interface. The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and PCS.

Figure 7. Reconfiguration Block
Related Information
Level Two Title