Visible to Intel only — GUID: qod1496699528186
Ixiasoft
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
Visible to Intel only — GUID: qod1496699528186
Ixiasoft
A. Difference between Stratix® 10 and Arria® 10 IP Variants
Feature | Stratix® 10 IP variant | Arria® 10 IP variant |
---|---|---|
GMII support for IGbE | - | Available |
IEEE 1588 support | - | Available |
Avalon® -MM Bus | Separate Avalon® -MM bus for IP registers and Native PHY IP core registers. | Single Avalon® -MM bus for IP registers and Native PHY IP core registers. |
Synopsys Design Constraints (SDC) | Available with IP generation. | Available with design example generation. |