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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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6.2.1. XGMII Mapping to Standard SDR XGMII Data
Signal Name | SDR XGMII Signal Name | Description |
---|---|---|
xgmii_tx_dc[7:0] | xgmii_sdr_data[7:0] | Lane 0 data |
xgmii_tx_dc[8] | xgmii_sdr_ctrl[0] | Lane 0 control |
xgmii_tx_dc[16:9] | xgmii_sdr_data[15:8] | Lane 1 data |
xgmii_tx_dc[17] | xgmii_sdr_ctrl[1] | Lane 1 control |
xgmii_tx_dc[25:18] | xgmii_sdr_data[23:16] | Lane 2 data |
xgmii_tx_dc[26] | xgmii_sdr_ctrl[2] | Lane 2 control |
xgmii_tx_dc[34:27] | xgmii_sdr_data[31:24] | Lane 3 data |
xgmii_tx_dc[35] | xgmii_sdr_ctrl[3] | Lane 3 control |
xgmii_tx_dc[43:36] | xgmii_sdr_data[39:32] | Lane 4 data |
xgmii_tx_dc[44] | xgmii_sdr_ctrl[4] | Lane 4 control |
xgmii_tx_dc[52:45] | xgmii_sdr_data[47:40] | Lane 5 data |
xgmii_tx_dc[53] | xgmii_sdr_ctrl[5] | Lane 5 control |
xgmii_tx_dc[61:54] | xgmii_sdr_data[55:48] | Lane 6 data |
xgmii_tx_dc[62] | xgmii_sdr_ctrl[6] | Lane 6 control |
xgmii_tx_dc[70:63] | xgmii_sdr_data[63:56] | Lane 7 data |
xgmii_tx_dc[71] | xgmii_sdr_ctrl[7] | Lane 7 control |
Signal Name | XGMII Signal Name | Description |
---|---|---|
xgmii_rx_dc[7:0] | xgmii_sdr_data[7:0] | Lane 0 data |
xgmii_rx_dc[8] | xgmii_sdr_ctrl[0] | Lane 0 control |
xgmii_rx_dc[16:9] | xgmii_sdr_data[15:8] | Lane 1 data |
xgmii_rx_dc[17] | xgmii_sdr_ctrl[1] | Lane 1 control |
xgmii_rx_dc[25:18] | xgmii_sdr_data[23:16] | Lane 2 data |
xgmii_rx_dc[26] | xgmii_sdr_ctrl[2] | Lane 2 control |
xgmii_rx_dc[34:27] | xgmii_sdr_data[31:24] | Lane 3 data |
xgmii_rx_dc[35] | xgmii_sdr_ctrl[3] | Lane 3 control |
xgmii_rx_dc[43:36] | xgmii_sdr_data[39:32] | Lane 4 data |
xgmii_rx_dc[44] | xgmii_sdr_ctrl[4] | Lane 4 control |
xgmii_rx_dc[52:45] | xgmii_sdr_data[47:40] | Lane 5 data |
xgmii_rx_dc[53] | xgmii_sdr_ctrl[5] | Lane 5 control |
xgmii_rx_dc[61:54] | xgmii_sdr_data[55:48] | Lane 6 data |
xgmii_rx_dc[62] | xgmii_sdr_ctrl[6] | Lane 6 control |
xgmii_rx_dc[70:63] | xgmii_sdr_data[63:56] | Lane 7 data |
xgmii_rx_dc[71] | xgmii_sdr_ctrl[7] | Lane 7 control |