Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.03 24.1 19.2.0 Made the following changes:
  • Updated resource utilization numbers due to changes from Nios® II to Nios® V.
  • Changed Nios® II to Nios® V in Stratix® 10 10GBASE-KR PHY IP Core Parameters: IP Tab.
2024.04.09 20.1 19.1.0
  • Updated the Stratix® 10 device family support to Final in Table: Device Family Support for LL 10GbE MAC.
  • Updated topic title Datasheet to About the Stratix® 10 10GBASE-KR PHY IP Core.
2021.01.29 20.1 19.1.0 Added Ethernet toolkit debugging tool description in the Supported Tools chapter.
2019.07.19 19.2 19.1.1
  • Stratix® 10 L-tile device support is now available for this IP in the current of the Quartus® Prime software.
  • Renamed the parameter Altera Debug Master Endpoint to Native PHY Debug Master Endpoint.
  • Added the following new parameters:
    • VCCR_GXB and VCCT_GXB supply voltage for the transceiver
    • Enable JTAG to Avalon Master Bridge
  • Modified the following commands in section Testing the Hardware Design Example:
    • reg_read to reconfig_read
    • reg_write to reconfig_write
2019.04.30 17.1 17.1
  • Clarified the supported core speed grade in section IP Core Speed Grade Support.
  • Made the following changes in Table: Test Harness Register Map:
    • Modified registers names:
      • XGMII rx_ready to rx_data_ready
      • XGMII test_done to test_done
    • Updated the description of the signals: rx_data_ready, XGMII_checker_pass, rx_mismatch, XGMII fifo_full, XGMII test_done, and XGMII frame_done.
    • Added new register XGMII RX frame_count channel 0
Date Version Changes
November 2017 2017.11.06
  • Updated for Quartus® Prime Pro Edition 17.1 release.
  • Added new chapter Getting Started explaining how to install, generate and integrate IP core in your design.
  • Added new chapter Design Example to demonstrate the functions of the IP core.
  • Updated device support for Stratix® 10 device with L-Tile transceivers in Table: Stratix® 10 10GBASE-KR PHY IP Core Device Family Support.
  • Changed chapter title from About Stratix® 10 10GBASE-KR PHY IP Core to Datasheet.
  • Modified chapter Datasheet to document the Stratix® 10 10GBASE-KR PHY IP Core Supported Features.
  • Updated description of Target Stratix-10 transceiver tile, Avalon® -MM clock frequency, and Link fail inhibit time for 10Gb Ethernet parameters in Table: Stratix® 10 10GBASE-KR PHY IP Core Parameters: IP Tab.
  • Added bits 2, 3, 18, 19, [22:20], [27:23], [31:38] to register address 0x4D0.
  • Corrected encoding for 1000BASE-KX and 10GBASE-KX4 mode of KR AN Link Ready [5:0] register.
  • Changed the register address 0x4B0 [8] to reserved.
  • Updated description of Tab PMA parameters in Table: Stratix® 10 10GBASE-KR PHY IP Core Parameters: IP Tab.
  • Corrected description of lcl_rf signal in Control and Status Signals section.
  • Removed signal reconfig_reset from Transceiver Reconfiguration Signals section.
  • Added new clock signal rx_div_clk in Clock and Reset Signals section.
  • Added VHDL simulation model support.
June 2017 2017.06.08 Initial release.
Level Two Title