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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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2.5.2. Adding the Transceiver PLL
Stratix® 10 10GBASE-KR PHY IP core requires an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.
The TX transceiver PLL is instantiated with an Intel FPGA ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the Stratix® 10 10GBASE-KR PHY IP core.
You can use the IP Catalog to create a transceiver PLL.
- Select Stratix 10 L-Tile/H-Tile Transceiver ATX PLL.
- In the parameter editor, set the following parameter values:
- PLL output frequency to 5156.25 MHz
- PLL auto mode reference clock frequency (integer) to 644.53125 MHz or 322.265625 MHz
You must connect the tx_serial_clk input pin of the Stratix® 10 10GBASE-KR IP core PHY link to the output port of the ATX PLL.