Visible to Intel only — GUID: wzk1501542653538
Ixiasoft
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
Visible to Intel only — GUID: wzk1501542653538
Ixiasoft
7.1.3. Simulation Design Example Components
The simulation design example top-level test file is testbench.v.
File Name | Description |
---|---|
Testbench and Simulation Files | |
testbench.v | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
Testbench Scripts | |
run_vsim.do | The Mentor Graphics ModelSim* script to run the testbench. |
run_vcs.sh | The Synopsys VCS* script to run the testbench. |
run_ncsim.sh | The Cadence NCSim* script to run the testbench. |