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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
Procedure
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
- Analyze the results. The successful testbench sends and receives XGMII, and displays "END OF TESTING"
Table 21. Steps to Simulate the Testbench Simulator Instructions ModelSim In the command line, type vsim -c -do run_vsim.do NCSim In the command line, type sh run_ncsim.sh VCS In the command line, type sh run_vcs.sh The following sample output illustrates a successful simulation test run:Start frame detected, byteslip 0, time 1362044322 Address 0x0000f002 data 0x00000053 Address 0x0000f004 data 0x000001a2 Address 0x0000f005 data 0x000001a2 Total BASER traffic cycle errors: 0 10G Traffic Test PASSED..!!! ** END OF TESTING... ** *****************************************