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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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7.1.6. Compiling and Configuring the Design Example in Hardware
To compile the hardware design example and configure it on your Stratix® 10 device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/de_wrapper.qpf.
- On the Processing menu, click Start Compilation.
- After you generate a SRAM object file (.sof), follow these steps to program the hardware design example on the Stratix® 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Stratix® 10 Transceiver Signal Integrity Development Kit to your Quartus® Prime session.
- Ensure that Mode is set to JTAG.
- Select the Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in Program/Configure column.
- Click Start.