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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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6.4. Avalon® -MM Interface Signals
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
mgmt_clk | Input | Clock | The clock signal that controls the Avalon-MM PHY management interface. This clock is used for both the PHY management interface and transceiver reconfiguration. You must restrict the frequency to a rate between 100 MHz and 161 MHz (inclusive) to meet the specification for the transceiver reconfiguration clock. |
mgmt_clk_reset | Input | Asynchronous reset | Resets the PHY management interface. This asynchronous signal is active high and level sensitive. |
mgmt_addr[10:0] | Input | Synchronous to mgmt_clk | 11-bit Avalon-MM address. |
mgmt_writedata[31:0] | Input | Synchronous to mgmt_clk | Input data. |
mgmt_readdata[31:0] | Output | Synchronous to mgmt_clk | Output data. |
mgmt_write | Input | Synchronous to mgmt_clk | Write signal. Active high. |
mgmt_read | Input | Synchronous to mgmt_clk | Read signal. Active high. |
mgmt_waitrequest | Output | Synchronous to mgmt_clk | When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant. |