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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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6.5. Transceiver Reconfiguration Signals
You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® -MM interface.
The Avalon® -MM interface implements a standard memory-mapped protocol. You can connect an Avalon master to this bus to access the registers of the embedded Transceiver PHY IP core.
Signal Name | Direction | Description |
---|---|---|
reconfig_write | Input | Write enable signal. Signal is active high. |
reconfig_read | Input | Read enable signal. Signal is active high. |
reconfig_address[10:0] | Input | Address bus. The lower 10 bits specify address and the upper bit specifies the channel (bit [10] is always 0) . |
reconfig_writedata[31:0] | Input | A 32-bit data write bus. reconfig_address specifies the address. |
reconfig_readdata[31:0] | Output | A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted. |
reconfig_waitrequest | Output | Indicates the Avalon® -MM interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted. |
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