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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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6.6. Control and Status Signals
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
rx_block_lock | Output | Synchronous to rx_clkout | When asserted, indicates the block synchronizer has established synchronization. |
rx_hi_ber | Output | Synchronous to rx_clkout | When asserted, indicates the BER monitor block detects a a Sync Header high bit error rate greater than 10-4. |
rx_is_lockedtodata | Output | Asynchronous signal | When asserted, indicates the RX channel is locked to input data. |
tx_cal_busy | Output | Synchronous to mgmt_clk | When asserted, indicates that the TX channel is being calibrated. |
rx_cal_busy | Output | Synchronous to mgmt_clk | When asserted, indicates that the RX channel is being calibrated. |
lcl_rf | Input | Synchronous to xgmii_tx_clk | When asserted, indicates a Remote Fault (RF).The MAC sends this fault signal to its link partner. This corresponds to bit D13 of the Auto Negotiation Link Codeword Base Page. |
rx_data_ready | Output | Synchronous to xgmii_rx_clk | When asserted, indicates that the MAC can begin sending data to the PHY. |
pcs_mode_rc [5:0] | Output | Synchronous to mgmt_clk | Specifies the PCS mode for reconfiguration. One-hot encoded. This signal has the following valid values:
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