Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Quartus® Prime Pro Edition 2. Quick Start Steps 3. Planning FPGA Design for RTL Flow 4. Working With Intel® FPGA IP Cores 5. Creating a New FPGA Design Project 6. Migrate Your FPGA Design Project 7. Managing Quartus® Prime Projects 8. Next Steps After Getting Started A. Using the Design Space Explorer II B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
1. Introduction to Quartus® Prime Pro Edition x
1.1. Before You Begin
1.1. Before You Begin x
1.1.1. Prerequisite Knowledge and Training 1.1.2. Navigate Content Through Tasks 1.1.3. Acronyms
3. Planning FPGA Design for RTL Flow x
3.1. Design Planning 3.2. Selecting the Design Methodology 3.3. Related Trainings
3.2. Selecting the Design Methodology x
3.2.1. Flat Design Vs. Incremental Block-based Design 3.2.2. Partial Reconfiguration Design
4. Working With Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 4.7. IP Core Generation Output ( Quartus® Prime Pro Edition) 4.8. Scripting IP Core Generation 4.9. Modifying an IP Variation 4.10. Upgrading IP Cores 4.11. Simulating Intel® FPGA IP Cores 4.12. Generating Simulation Files for Platform Designer Systems and IP Variants 4.13. Synthesizing IP Cores in Other EDA Tools 4.14. Instantiating IP Cores in HDL 4.15. Support for the IEEE 1735 Encryption Standard 4.16. Related Trainings and Resources
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
4.6.1. Applying Preset Parameters for Specific Applications 4.6.2. Customizing IP Presets
4.6.1. Applying Preset Parameters for Specific Applications x
4.6.1.1. Viewing, Applying, and Deleting IP Presets
4.6.2. Customizing IP Presets x
4.6.2.1. Defining Preset Pin Assignments
4.6.2.1. Defining Preset Pin Assignments x
4.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 4.6.2.1.2. Defining Preset Pin Assignments in a Pin File
4.10. Upgrading IP Cores x
4.10.1. Upgrading IP Cores at Command-Line 4.10.2. Migrating IP Cores to a Different Device 4.10.3. Troubleshooting IP or Platform Designer System Upgrade
4.11. Simulating Intel® FPGA IP Cores x
4.11.1. Generating IP Simulation Files 4.11.2. Scripting IP Simulation
4.11.2. Scripting IP Simulation x
4.11.2.1. Generating a Combined Simulator Setup Script
4.14. Instantiating IP Cores in HDL x
4.14.1. Example Top-Level Verilog HDL Module 4.14.2. Example Top-Level VHDL Module
5. Creating a New FPGA Design Project x
5.1. Using the Board-Aware Flow
5.1. Using the Board-Aware Flow x
5.1.1. Creating a New Project from a Design Example 5.1.2. Specifying a Target Board for the Project
5.1.1. Creating a New Project from a Design Example x
5.1.1.1. Family, Device & Board Settings 5.1.1.2. Accessing Pre-Installed Design Examples 5.1.1.3. Accessing Online Design Examples 5.1.1.4. Accessing Downloaded Design Examples
5.1.1.3. Accessing Online Design Examples x
5.1.1.3.1. Internet Connectivity Options 5.1.1.3.2. Design Examples Options
6. Migrate Your FPGA Design Project x
6.1. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition 6.2. Migrating Your AMD* Vivado* Project to Quartus® Prime Pro Edition 6.3. Migrating Projects Across Operating Systems 6.4. Migrating Project From One Device to Another 6.5. Related Trainings
6.1. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition x
6.1.1. Keeping Pro Edition Project Files Separate 6.1.2. Upgrading Project Assignments and Constraints 6.1.3. Upgrading IP Cores and Platform Designer Systems 6.1.4. Upgrading Non-Compliant Design RTL
6.1.2. Upgrading Project Assignments and Constraints x
6.1.2.1. Modifying Entity Name Assignments 6.1.2.2. Resolving Timing Constraint Entity Names 6.1.2.3. Verifying Generated Node Name Assignments 6.1.2.4. Replace Logic Lock (Standard) Regions 6.1.2.5. Modifying Signal Tap Logic Analyzer Files 6.1.2.6. Removing References to .qip Files 6.1.2.7. Removing Unsupported Feature Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions x
6.1.2.4.1. Logic Lock Region Assignment Examples
6.1.4. Upgrading Non-Compliant Design RTL x
6.1.4.1. Verifying Verilog Compilation Unit 6.1.4.2. Updating Entity Auto-Discovery 6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library 6.1.4.4. Removing Unsupported Parameter Passing 6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation 6.1.4.6. Removing Non-Standard Pragmas 6.1.4.7. Declaring Objects Before Initial Values 6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files 6.1.4.9. Avoiding Assignment Mixing in Always Blocks 6.1.4.10. Avoiding Unconnected, Non-Existent Ports 6.1.4.11. Avoiding Invalid Parameter Ranges 6.1.4.12. Updating Verilog HDL and VHDL Type Mapping 6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
6.1.4.1. Verifying Verilog Compilation Unit x
6.1.4.1.1. Verilog HDL Configuration Instantiation
6.3. Migrating Projects Across Operating Systems x
6.3.1. Migrating Design Files and Libraries 6.3.2. Design Library Migration Guidelines
6.3.1. Migrating Design Files and Libraries x
6.3.1.1. Use Relative Paths
7. Managing Quartus® Prime Projects x
7.1. Viewing Basic Project Information 7.2. Managing Project Settings 7.3. Viewing Parameter Settings From the Project Navigator 7.4. Managing Logic Design Files 7.5. Managing Timing Constraints 7.6. Integrating Other EDA Tools 7.7. Exporting Compilation Results 7.8. Archiving Projects 7.9. Command-Line Interface 7.10. Related Trainings
7.1. Viewing Basic Project Information x
7.1.1. Using the Compilation Dashboard 7.1.2. Exploring Quartus® Prime Project Contents 7.1.3. Viewing Design Hierarchy and Adding Missing Source Files 7.1.4. Viewing Project Reports 7.1.5. Viewing Project Messages
7.1.2. Exploring Quartus® Prime Project Contents x
7.1.2.1. Project File Best Practices
7.1.5. Viewing Project Messages x
7.1.5.1. Viewing Synthesis Warning Messages 7.1.5.2. Suppressing Message Display 7.1.5.3. Promoting Critical Warnings to Errors
7.4. Managing Logic Design Files x
7.4.1. Including Design Libraries 7.4.2. Creating a Project Copy
7.7. Exporting Compilation Results x
7.7.1. Exporting a Version-Compatible Compilation Database 7.7.2. Importing a Version-Compatible Compilation Database 7.7.3. Creating a Design Partition 7.7.4. Exporting a Design Partition 7.7.5. Reusing a Design Partition 7.7.6. Viewing Quartus Database File Information 7.7.7. Clearing Compilation Results
7.7.6. Viewing Quartus Database File Information x
7.7.6.1. QDB File Attribute Types
7.8. Archiving Projects x
7.8.1. Manually Adding Files To Archives 7.8.2. Archiving Projects for Service Requests 7.8.3. Archiving Projects for External Revision Control 7.8.4. Creating Database-Only Archives
7.8.3. Archiving Projects for External Revision Control x
7.8.3.1. Project Files to Include In External Revision Control
7.9. Command-Line Interface x
7.9.1. Project Revision Commands 7.9.2. Project Archive Commands 7.9.3. Project Database Commands
7.9.3. Project Database Commands x
7.9.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
8. Next Steps After Getting Started x
8.1. Additional Resources 8.2. Training
A. Using the Design Space Explorer II x
A.1. Optimizing Project Settings A.2. Running DSE II A.3. Setting Up Remote Farm Using Design Space Explorer II
A.1. Optimizing Project Settings x
A.1.1. Optimizing Settings with Design Space Explorer II A.1.2. Optimizing Settings with Project Revisions A.1.3. Back-Annotating Optimized Assignments
A.1.1. Optimizing Settings with Design Space Explorer II x
A.1.1.1. DSE II Computing Resources A.1.1.2. DSE II Optimization Parameters A.1.1.3. DSE II Result Management
Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started

A.3. Setting Up Remote Farm Using Design Space Explorer II

To launch Design Space Explorer II, in the Quartus® Prime Pro Edition GUI, click Tools > Launch Design Space Explorer II. Click Yes to the message that appears. This closes the Quartus® Prime software and launches the Design Space Explorer II.
Under the Project tab, click Open Project to add your project to the Design Space Explorer II. Refer to Project Page (Design Space Explorer II) for information about all options on this tab.
Use one of the following methods to set up your remote farm:

LSF Remote Farm

Follow these steps to set up your remote machine using the Design Space Explorer II and LSF remote compilation type:

  1. Ensure you have set up your LSF environment. If not, request your IT administrator to set up the LSF environment.
  2. Once the LSF environment is ready, launch the command line interface and execute the bsub sleep 60 command.
  3. Under the Setup tab, select Remote compilation type and choose the LSF option from the drop-down list. Populate all mandatory settings under Specify custom settings for LSF with the LSF environment-specific information.

    Refer to Setup Page (Design Space Explorer II) for information about all options on this tab.

  4. Customize the settings as necessary.
  5. Under the Exploration tab, expand the Exploration Points section.
  6. Select Design exploration.
  7. Under Exploration Options, select Seed Sweep Only.
  8. Under Seeds, select Create. By default, it must be set to 2 seeds.
  9. Click Start. Wait until the design exploration is complete.
  10. Click the Results tab to review the status of the design exploration.

SSH Remote Farm

Follow these steps to set up your remote machine using the Design Space Explorer II and SSH remote compilation type:

  1. Install the open-source PuTTY Key Generator tool and launch it.
  2. Click Generate to generate the public/private key pair.
  3. Enter the key passphrase.
  4. Click Save private key to save the private key with a .ppk extension.
  5. Click Save public key to save the public key as putty_gen_public_key.pub.
  6. On your machine, change to the SSH directory and copy the contents of the putty_gen_public_key.pub file.
  7. In the Design Space, under the Setup tab, select SSH compilation type and specify the following:
    • For Hostname, enter the server name.
    • For private_key, enter the path to your private key (.ppk file).
    • For SSH Client, enter the path to the plink.exe file. You can find this in the same directory where you installed the PuTTy tool.
    • For Farm Operating System, enter your system type (linux or windows).

    The remaining settings are similar to LSF settings. Refer to Setup Page (Design Space Explorer II) for information about all options on this tab.

  8. Under the Exploration tab, expand the Exploration Points section.
  9. Select Design exploration.
  10. Under Exploration Options, select Seed Sweep Only.
  11. Under Seeds, select Create. By default, it must be set to 2 seeds.
  12. Click Start. Wait until the design exploration is complete.
  13. Click the Results tab to review the status of the design exploration.
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