Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 7/08/2024
Public
Document Table of Contents

B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started

Document Version Quartus® Prime Version Changes
2024.07.08 24.2
  • Updated the image in Archiving Projects for Service Requests.
  • Added Quick Start Steps chapter.
  • Updated the compilation board image in Using the Compilation Dashboard.
  • Updated the version-compatible compilation database support table in Exporting a Version-compatible Compilation Database.
  • Revised the instructions in Generating Simulation Files for Platform Designer Systems and IP Variants.
  • Revised the Location column of the table in IP General Settings.
  • Added note about requirement to create and modify IP preset pin assignments only in Platform Designer to Customizing IP Presets and Defining Preset Pin Assignments topics.
2024.04.01 24.1
  • Made the following updates in Introduction to Quartus® Prime Pro Edition :
    • Included additional steps to the quick start table.
    • Updated the Quartus® Prime software main page image in the table.
    • Updated the support matrix image to include Agilex™ 5 device support.
    • Updated supported features table to include Agilex™ 5 device support for hyper-aware design flow.
    • Updated the Intel FPGA developmental tools table to include Agilex™ 5 device support for PTC.
  • Revised prerequisite training list in Prerequisite Knowledge and Training.
  • Consolidated the information of design planning into a table in Planning FPGA Design for RTL Flow.
  • Added Viewing Design Hierarchy and Adding Missing Source Files.
  • Removed the Quartus® Prime software main page image in Creating a New FPGA Design Project.
  • Revised the IP version upgrade path image in Upgrading IP Cores.
  • Revised Generating IP Simulation Files topic entirely.
  • Revised the note about .bdf files in Managing Logic Design Files.
2023.12.04 23.4
  • Made major reorganization of chapters and topics.
  • Added additional information to Introduction to Quartus® Prime Pro Edition .
  • Renamed FPGA Basic Design Prerequisites as Prerequisite Knowledge and Training and included a list of trainings.
  • Revised the information for accessing online design examples in Creating a New Project from a Design Example.
  • Renamed the chapter title "Design Planning" to "Planning FPGA Design for RTL Flow."
  • Renamed the topic "Plan for Hierarchical and Team-Based Designs" to "Selecting the Design Methodology."
  • Added the following:
    • Before You Begin
    • Acronyms
    • Navigate Content Through Tasks
    • Selecting the Design Methodology
    • Flat Design Vs. Incremental Block-based Design
    • Partial Reconfiguration Design
    • Related Trainings
    • Migrating Your AMD* Vivado* Project to Quartus® Prime Pro Edition
    • Migrating Project From One Device to Another
    • Converting Symbolic BDF Files to Acceptable File Formats
    • Project Path Length Considerations
  • Renamed the chapter name from Migrating to Quartus® Prime Pro Edition to Selecting a Starting Point for Your Quartus® Prime Pro Edition Project.
  • Moved Creating a New FPGA Design Project, Migrating Projects Across Operating Systems and their subtopics from Managing Quartus® Prime Projects chapter to this chapter.
  • Chapter renamed as "Working With Intel® FPGA IP Cores."
  • Removed the following topics and added a reference to Quartus® Prime Pro Edition User Guide: Third-party Simulation where these topics are explained in detail.
    • Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
    • Sourcing Cadence Incisive* Simulator Setup Scripts
    • Sourcing Cadence Xcelium Simulator Setup Scripts
    • Sourcing QuestaSim* Simulator Setup Scripts
    • Sourcing Synopsys VCS Simulator Setup Scripts
    • Sourcing Synopsys VCS MX Simulator Setup Scripts
  • Moved Creating a New FPGA Design Project, Migrating Projects Across Operating Systems and their subtopics to Selecting a Starting Point for Your Quartus® Prime Pro Edition Project chapter.
  • In Managing Logic Design Files, added information about converting .bdf to .v or .vhd file.
  • Removed "Block Diagram/Schematic Design Files (.bdf)" in Project Files to Include In External Revision Control.
  • Added Viewing Parameter Settings From the Project Navigator.
  • Added an appendix about Using Design Space Explorer II and included related topics.
  • Revised the Power and Thermal Calculator (PTC) image in Planning for Device Power Consumption.
2023.10.02 23.3
  • Updated the compilation dashboard image in Introduction to Quartus® Prime Pro Edition and Using the Compilation Dashboard.
  • Removed OpenCL support from the "Intel Quartus Prime Feature Support Matrix" image in Selecting an Quartus® Prime Software Edition.
  • Made a minor correction in Logic Lock Region Assignment Examples.
  • Revised the " Quartus® Prime Pro Edition IP Version Upgrade Paths" image in Upgrading IP Cores.
  • Updated the dashboard image in Using the Compilation Dashboard.
2023.06.26 23.2
  • Updated Power Analyzer Settings screenshot for new settings name.
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
  • Added note to Upgrade Project Assignments and Constraints about new prompt to update operating temperatures in a migrated project.
  • Updated Support for the IEEE 1735 Encryption Standard topic for new installed location of public encryption key.
  • Updated Intel Quartus Prime Pro Edition IP Version Upgrade Paths support chart.
2022.12.12 22.4
  • Updated Plan for the Target Device or Board topic for board-aware features.
  • Revised Applying Preset Parameters for Specific Applications topic for board-aware features.
  • Added new Viewing, Applying, and Deleting IP Presets topic.
  • Added new Example IP Preset File (.qprs) topic.
  • Revised Customizing IP Presets topic for board-aware features.
  • Added new Defining Preset Pin Assignments section.
  • Revised Creating a New FPGA Design Project for board-aware features.
  • Added Using the Board-Aware Flow topic.
  • Added Creating a New Project from a Design Example topic.
  • Added Family, Device & Board Settings topic.
  • Added Accessing Pre-Installed Design Examples topic.
  • Added Accessing Online Design Examples topic.
  • Added Accessing Downloaded Design Examples topic.
  • Added Internet Connectivity Options topic.
  • Added Design Examples Options topic.
  • Added Specifying a Target Board for the Project topic.
2022.06.20 22.2
  • Added new Top FAQs navigation to document cover.
  • Revised Introduction to add FPGA definition and device selection footnote.
  • Added new FPGA Basic Design Prerequisites topic.
  • Added new Experiment with a Design Example topic.
  • Removed obsolete Simultaneous Switching Noise Analysis topic from this basic discussion.
2022.03.28 22.1
  • Added information about Power and Thermal Calculator in Plan for Device Power Consumption.
  • Removed references to obsolete Advisors from Optimizing Project Settings topic.
  • Added Viewing Synthesis Warning Messages topic.
  • Removed the topic Automated Problem Reports.
2021.10.04 21.3
  • Added support for Questa*-Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
  • Updated Quartus® Prime Pro Edition IP Version Upgrade Paths figure for latest versions.
2021.06.21 21.2
  • Added Version-Compatible Compilation Database Support table.
  • Added "Promoting Critical Warnings to Errors" topic.
2021.03.29 21.1
  • Enhanced Simulating Intel FPGA Designs topic with screenshot, links, and additional contextual details.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Revised Using the EDA Netlist Writer wording for clarity.
  • Added "Creating Database-Only Archives" topic.
  • Added "Promoting Critical Warnings to Errors" topic
2020.11.09 20.3
  • Revised "Introduction to Intel FPGA IP Cores" topic to include Bridges and Adapters and Intel FPGA Interconnect categories in IP Catalog. Updated IP Catalog image.
  • Revised wording of "Intel FPGA IP Versioning" topic for clarity.
  • Added screenshot to "Checking the IP License Status" topic.
  • Added "IP Version Upgrade Paths" diagram to "Upgrading IP Cores" topic.
  • Updated IP Port Differences Report image in "Troubleshooting IP or System Upgrade" topic.
2020.09.28 20.3
  • Updated GUI screenshot in Introduction.
  • Updated "Back-Annotate Optimized Assignments" for support of pins, clocks, RAMs, and DSPs.
2020.05.01 20.1
  • Added note about .qar file requirements to "Design Guidelines for Component Instances" topic.
2019.09.30 19.3
  • Added compilation support for Agilex™ 7 devices.
  • Added "Checking the IP License Status" topic.
  • Added details to "Support for the IEEE 1735 Encryption Standard."
  • Added Intel® FPGA IP Versioning" topic.
  • Added "Disabling Automated Problem Reports" topic.
  • Added "Suppressing Messages" topic.
2019.05.13 18.1
  • Added archives topic.
  • Updated the keyname and added --help information to "Support for the IEEE 1735 Encryption Standard."
2018.10.24 18.1
  • Updated information about obtaining IEEE 1735 Encryption key.
2018.09.24 18.1
  • Added screenshot of Quartus® Prime Pro Edition GUI.
  • Moved information about specifying the target board to "Specifying the Target Device or Board" in Managing Projects chapter.
  • Retitled "Creating Design Specifications" to "Create a Design Specification and Test Plan."
  • Retitled "Selecting Intellectual Property Cores" to "Plan for Intellectual Property Cores."
  • Retitled "Using Standard Interfaces" to "Plan for Standard Interfaces." Corrected references to Platform Designer.
  • Retitled "Device Selection" to "Plan for the Target Device." Updated this content to correct Platform Designer names.
  • Moved "Setting Pin Assignments" to Managing Projects chapter as "Generating Pin Assignments for a Target Board."
  • Retitled "Estimating Power" to "Plan for Device Power Consumption." Reorganized this topic into sections for EPE and Power Analyzer.
  • Added link to "Simulator Support, Third-Party Simulation User Guide
  • Retitled "Planning for Device Programming or Configuration" to "Plan for Device Programming"
  • Retitled "Selecting Third-Party EDA Tools" to "Plan for other EDA Tools."
  • Retitled "Planning for On-Chip Debugging Tools" to "Plan for On-Chip Debugging Tools."
  • Retitled Design Planning with the Intel Quartus Prime Software to Design Planning
  • Added information about removing assignments from the qsf file that point to legacy output files.
  • Added statement that the Quartus® Prime software installer does not support spaces in the installation path.
  • Added "Intel FPGA IP Best Practices" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter of Getting Started User Guide.
  • Subdivided "Exporting, Archiving, and Migrating Projects" into separate sections.
  • Described migration of full chip database in "Exporting a Version-Compatible Compilation Database" topic.
  • Described automated .qdb partition export in "Exporting a Design Partition" topic.
  • Added "Viewing Quartus Database File Information" topic.
  • Added "Specifying the Target Device or Board" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter.
  • Moved "IP Core Best Practices" topic to Introduction to Intel FPGA IP Cores chapter.
  • Moved "Factors Affecting Compilation Results" topic to Design Compilation: Intel Quartus Prime Pro Edition User Guide.
2018.05.07 18.0
  • Initial release as separate chapter of Getting Started User Guide. Separated Migrating to Quartus® Prime Pro Edition as independent chapter in user guide.
  • Initial release as separate chapter of Getting Started User Guide. Separated Design Planning as independent chapter in user guide.
  • Initial release as separate chapter of Getting Started User Guide. Separated Introduction to Intel® FPGA IP Cores as independent chapter in user guide.
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
  • Added note about Generate Combined Simulator Setup Scripts command limitations.
  • Added information about generation of simulation files for Xcelium*
  • Initial release as chapter of Getting Started User Guide.
  • Revised "Exporting a Design Partition" topic to add Include entity-bound SDC files for the selected partition option, to add prerequisite steps, and to remove import step covered in separate topic.
  • Changed title of "Managing Team-Based Designs" to "Exporting, Archiving, and Migrating Projects" and updated content.
  • Changed title of "Migrating Compilation Results Across Software Versions" to "Exporting the Compilation Database" and updated content.
  • Changed title of "Exporting the Results Database" to "Exporting a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Importing the Results Database" to "Importing a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Cleaning the Project Database" to "Cleaning the Project Compilation Database."
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
2017.11.06 17.1
  • Described Quartus® Prime tool name updates for Platform Designer (Qsys), Interface Planner (BluePrint), Timing Analyzer (TimeQuest), Eye Viewer (EyeQ), and Intel® Advanced Link Analyzer (Advanced Link Analyzer).
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
  • Revised product branding for Intel® standards.
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
2017.05.08 17.0
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
  • Added reference to Block-Based Design Flows.
  • Removed procedure on manual dynamic synthesis report generation. The Compiler automatically generates dynamic synthesis reports when enabled.
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
  • Added note that IP core encryption is supported only in Quartus® Prime Pro Edition.
  • Revised product branding for Intel® standards.
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Added reference to Partial Reconfiguration support.
  • Added to list of Quartus® Prime Standard Edition features unsupported by Quartus® Prime Pro Edition.
  • Added topic on Safe State Machine encoding.
  • Described unsupported Quartus® Prime Standard Edition physical synthesis options.
  • Removed deprecated Per-Stage Compilation (Beta) Compilation Flow.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
  • Implemented Intel rebranding.
  • Described unsupported Quartus® Prime Standard Edition physical synthesis options.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
  • Removed references to .qsys file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Added references to .ip file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Updated IP Core Generation Output files list and diagram.
  • Indicated distinctions between Quartus® Prime Pro Edition and Quartus® Prime Standard Edition features.
  • Added Support for IP Core Encryption topic.
2016.05.03 16.0
  • Removed software beta status and revised feature set.
  • Added topic on Safe State Machine encoding.
  • Added Generating Dynamic Synthesis Reports.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Added description of Fitter Plan, Place and Route stages, reporting, and optimization.
  • Added Per-Stage Compilation (Beta) Compilation Flow.
  • Added Platform Designer information.
  • Added OpenCL and Signal Tap with routing preservation as unique Pro Edition features.
  • Clarified limitations for multiple Logic Lock instances in the same region.
  • Added topic on Safe State Machine encoding.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Clarified limitations for multiple Logic Lock instances in the same region.
2015.11.02 15.1
  • First version of document.