Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Quartus® Prime Pro Edition 2. Quick Start Steps 3. Planning FPGA Design for RTL Flow 4. Working With Intel® FPGA IP Cores 5. Creating a New FPGA Design Project 6. Migrate Your FPGA Design Project 7. Managing Quartus® Prime Projects 8. Next Steps After Getting Started A. Using the Design Space Explorer II B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
1. Introduction to Quartus® Prime Pro Edition x
1.1. Before You Begin
1.1. Before You Begin x
1.1.1. Prerequisite Knowledge and Training 1.1.2. Navigate Content Through Tasks 1.1.3. Acronyms
3. Planning FPGA Design for RTL Flow x
3.1. Design Planning 3.2. Selecting the Design Methodology 3.3. Related Trainings
3.2. Selecting the Design Methodology x
3.2.1. Flat Design Vs. Incremental Block-based Design 3.2.2. Partial Reconfiguration Design
4. Working With Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 4.7. IP Core Generation Output ( Quartus® Prime Pro Edition) 4.8. Scripting IP Core Generation 4.9. Modifying an IP Variation 4.10. Upgrading IP Cores 4.11. Simulating Intel® FPGA IP Cores 4.12. Generating Simulation Files for Platform Designer Systems and IP Variants 4.13. Synthesizing IP Cores in Other EDA Tools 4.14. Instantiating IP Cores in HDL 4.15. Support for the IEEE 1735 Encryption Standard 4.16. Related Trainings and Resources
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
4.6.1. Applying Preset Parameters for Specific Applications 4.6.2. Customizing IP Presets
4.6.1. Applying Preset Parameters for Specific Applications x
4.6.1.1. Viewing, Applying, and Deleting IP Presets
4.6.2. Customizing IP Presets x
4.6.2.1. Defining Preset Pin Assignments
4.6.2.1. Defining Preset Pin Assignments x
4.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 4.6.2.1.2. Defining Preset Pin Assignments in a Pin File
4.10. Upgrading IP Cores x
4.10.1. Upgrading IP Cores at Command-Line 4.10.2. Migrating IP Cores to a Different Device 4.10.3. Troubleshooting IP or Platform Designer System Upgrade
4.11. Simulating Intel® FPGA IP Cores x
4.11.1. Generating IP Simulation Files 4.11.2. Scripting IP Simulation
4.11.2. Scripting IP Simulation x
4.11.2.1. Generating a Combined Simulator Setup Script
4.14. Instantiating IP Cores in HDL x
4.14.1. Example Top-Level Verilog HDL Module 4.14.2. Example Top-Level VHDL Module
5. Creating a New FPGA Design Project x
5.1. Using the Board-Aware Flow
5.1. Using the Board-Aware Flow x
5.1.1. Creating a New Project from a Design Example 5.1.2. Specifying a Target Board for the Project
5.1.1. Creating a New Project from a Design Example x
5.1.1.1. Family, Device & Board Settings 5.1.1.2. Accessing Pre-Installed Design Examples 5.1.1.3. Accessing Online Design Examples 5.1.1.4. Accessing Downloaded Design Examples
5.1.1.3. Accessing Online Design Examples x
5.1.1.3.1. Internet Connectivity Options 5.1.1.3.2. Design Examples Options
6. Migrate Your FPGA Design Project x
6.1. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition 6.2. Migrating Your AMD* Vivado* Project to Quartus® Prime Pro Edition 6.3. Migrating Projects Across Operating Systems 6.4. Migrating Project From One Device to Another 6.5. Related Trainings
6.1. Migrating Projects from Other Quartus® Prime Editions to Quartus® Prime Pro Edition x
6.1.1. Keeping Pro Edition Project Files Separate 6.1.2. Upgrading Project Assignments and Constraints 6.1.3. Upgrading IP Cores and Platform Designer Systems 6.1.4. Upgrading Non-Compliant Design RTL
6.1.2. Upgrading Project Assignments and Constraints x
6.1.2.1. Modifying Entity Name Assignments 6.1.2.2. Resolving Timing Constraint Entity Names 6.1.2.3. Verifying Generated Node Name Assignments 6.1.2.4. Replace Logic Lock (Standard) Regions 6.1.2.5. Modifying Signal Tap Logic Analyzer Files 6.1.2.6. Removing References to .qip Files 6.1.2.7. Removing Unsupported Feature Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions x
6.1.2.4.1. Logic Lock Region Assignment Examples
6.1.4. Upgrading Non-Compliant Design RTL x
6.1.4.1. Verifying Verilog Compilation Unit 6.1.4.2. Updating Entity Auto-Discovery 6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library 6.1.4.4. Removing Unsupported Parameter Passing 6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation 6.1.4.6. Removing Non-Standard Pragmas 6.1.4.7. Declaring Objects Before Initial Values 6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files 6.1.4.9. Avoiding Assignment Mixing in Always Blocks 6.1.4.10. Avoiding Unconnected, Non-Existent Ports 6.1.4.11. Avoiding Invalid Parameter Ranges 6.1.4.12. Updating Verilog HDL and VHDL Type Mapping 6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
6.1.4.1. Verifying Verilog Compilation Unit x
6.1.4.1.1. Verilog HDL Configuration Instantiation
6.3. Migrating Projects Across Operating Systems x
6.3.1. Migrating Design Files and Libraries 6.3.2. Design Library Migration Guidelines
6.3.1. Migrating Design Files and Libraries x
6.3.1.1. Use Relative Paths
7. Managing Quartus® Prime Projects x
7.1. Viewing Basic Project Information 7.2. Managing Project Settings 7.3. Viewing Parameter Settings From the Project Navigator 7.4. Managing Logic Design Files 7.5. Managing Timing Constraints 7.6. Integrating Other EDA Tools 7.7. Exporting Compilation Results 7.8. Archiving Projects 7.9. Command-Line Interface 7.10. Related Trainings
7.1. Viewing Basic Project Information x
7.1.1. Using the Compilation Dashboard 7.1.2. Exploring Quartus® Prime Project Contents 7.1.3. Viewing Design Hierarchy and Adding Missing Source Files 7.1.4. Viewing Project Reports 7.1.5. Viewing Project Messages
7.1.2. Exploring Quartus® Prime Project Contents x
7.1.2.1. Project File Best Practices
7.1.5. Viewing Project Messages x
7.1.5.1. Viewing Synthesis Warning Messages 7.1.5.2. Suppressing Message Display 7.1.5.3. Promoting Critical Warnings to Errors
7.4. Managing Logic Design Files x
7.4.1. Including Design Libraries 7.4.2. Creating a Project Copy
7.7. Exporting Compilation Results x
7.7.1. Exporting a Version-Compatible Compilation Database 7.7.2. Importing a Version-Compatible Compilation Database 7.7.3. Creating a Design Partition 7.7.4. Exporting a Design Partition 7.7.5. Reusing a Design Partition 7.7.6. Viewing Quartus Database File Information 7.7.7. Clearing Compilation Results
7.7.6. Viewing Quartus Database File Information x
7.7.6.1. QDB File Attribute Types
7.8. Archiving Projects x
7.8.1. Manually Adding Files To Archives 7.8.2. Archiving Projects for Service Requests 7.8.3. Archiving Projects for External Revision Control 7.8.4. Creating Database-Only Archives
7.8.3. Archiving Projects for External Revision Control x
7.8.3.1. Project Files to Include In External Revision Control
7.9. Command-Line Interface x
7.9.1. Project Revision Commands 7.9.2. Project Archive Commands 7.9.3. Project Database Commands
7.9.3. Project Database Commands x
7.9.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
8. Next Steps After Getting Started x
8.1. Additional Resources 8.2. Training
A. Using the Design Space Explorer II x
A.1. Optimizing Project Settings A.2. Running DSE II A.3. Setting Up Remote Farm Using Design Space Explorer II
A.1. Optimizing Project Settings x
A.1.1. Optimizing Settings with Design Space Explorer II A.1.2. Optimizing Settings with Project Revisions A.1.3. Back-Annotating Optimized Assignments
A.1.1. Optimizing Settings with Design Space Explorer II x
A.1.1.1. DSE II Computing Resources A.1.1.2. DSE II Optimization Parameters A.1.1.3. DSE II Result Management
Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started

B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started

Document Version Quartus® Prime Version Changes
2024.07.08 24.2
  • Updated the image in Archiving Projects for Service Requests.
  • Added Quick Start Steps chapter.
  • Updated the compilation board image in Using the Compilation Dashboard.
  • Updated the version-compatible compilation database support table in Exporting a Version-compatible Compilation Database.
  • Revised the instructions in Generating Simulation Files for Platform Designer Systems and IP Variants.
  • Revised the Location column of the table in IP General Settings.
  • Added note about requirement to create and modify IP preset pin assignments only in Platform Designer to Customizing IP Presets and Defining Preset Pin Assignments topics.
2024.04.01 24.1
  • Made the following updates in Introduction to Quartus® Prime Pro Edition :
    • Included additional steps to the quick start table.
    • Updated the Quartus® Prime software main page image in the table.
    • Updated the support matrix image to include Agilex™ 5 device support.
    • Updated supported features table to include Agilex™ 5 device support for hyper-aware design flow.
    • Updated the Intel FPGA developmental tools table to include Agilex™ 5 device support for PTC.
  • Revised prerequisite training list in Prerequisite Knowledge and Training.
  • Consolidated the information of design planning into a table in Planning FPGA Design for RTL Flow.
  • Added Viewing Design Hierarchy and Adding Missing Source Files.
  • Removed the Quartus® Prime software main page image in Creating a New FPGA Design Project.
  • Revised the IP version upgrade path image in Upgrading IP Cores.
  • Revised Generating IP Simulation Files topic entirely.
  • Revised the note about .bdf files in Managing Logic Design Files.
2023.12.04 23.4
  • Made major reorganization of chapters and topics.
  • Added additional information to Introduction to Quartus® Prime Pro Edition .
  • Renamed FPGA Basic Design Prerequisites as Prerequisite Knowledge and Training and included a list of trainings.
  • Revised the information for accessing online design examples in Creating a New Project from a Design Example.
  • Renamed the chapter title "Design Planning" to "Planning FPGA Design for RTL Flow."
  • Renamed the topic "Plan for Hierarchical and Team-Based Designs" to "Selecting the Design Methodology."
  • Added the following:
    • Before You Begin
    • Acronyms
    • Navigate Content Through Tasks
    • Selecting the Design Methodology
    • Flat Design Vs. Incremental Block-based Design
    • Partial Reconfiguration Design
    • Related Trainings
    • Migrating Your AMD* Vivado* Project to Quartus® Prime Pro Edition
    • Migrating Project From One Device to Another
    • Converting Symbolic BDF Files to Acceptable File Formats
    • Project Path Length Considerations
  • Renamed the chapter name from Migrating to Quartus® Prime Pro Edition to Selecting a Starting Point for Your Quartus® Prime Pro Edition Project.
  • Moved Creating a New FPGA Design Project, Migrating Projects Across Operating Systems and their subtopics from Managing Quartus® Prime Projects chapter to this chapter.
  • Chapter renamed as "Working With Intel® FPGA IP Cores."
  • Removed the following topics and added a reference to Quartus® Prime Pro Edition User Guide: Third-party Simulation where these topics are explained in detail.
    • Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
    • Sourcing Cadence Incisive* Simulator Setup Scripts
    • Sourcing Cadence Xcelium Simulator Setup Scripts
    • Sourcing QuestaSim* Simulator Setup Scripts
    • Sourcing Synopsys VCS Simulator Setup Scripts
    • Sourcing Synopsys VCS MX Simulator Setup Scripts
  • Moved Creating a New FPGA Design Project, Migrating Projects Across Operating Systems and their subtopics to Selecting a Starting Point for Your Quartus® Prime Pro Edition Project chapter.
  • In Managing Logic Design Files, added information about converting .bdf to .v or .vhd file.
  • Removed "Block Diagram/Schematic Design Files (.bdf)" in Project Files to Include In External Revision Control.
  • Added Viewing Parameter Settings From the Project Navigator.
  • Added an appendix about Using Design Space Explorer II and included related topics.
  • Revised the Power and Thermal Calculator (PTC) image in Planning for Device Power Consumption.
2023.10.02 23.3
  • Updated the compilation dashboard image in Introduction to Quartus® Prime Pro Edition and Using the Compilation Dashboard.
  • Removed OpenCL support from the "Intel Quartus Prime Feature Support Matrix" image in Selecting an Quartus® Prime Software Edition.
  • Made a minor correction in Logic Lock Region Assignment Examples.
  • Revised the " Quartus® Prime Pro Edition IP Version Upgrade Paths" image in Upgrading IP Cores.
  • Updated the dashboard image in Using the Compilation Dashboard.
2023.06.26 23.2
  • Updated Power Analyzer Settings screenshot for new settings name.
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
  • Added note to Upgrade Project Assignments and Constraints about new prompt to update operating temperatures in a migrated project.
  • Updated Support for the IEEE 1735 Encryption Standard topic for new installed location of public encryption key.
  • Updated Intel Quartus Prime Pro Edition IP Version Upgrade Paths support chart.
2022.12.12 22.4
  • Updated Plan for the Target Device or Board topic for board-aware features.
  • Revised Applying Preset Parameters for Specific Applications topic for board-aware features.
  • Added new Viewing, Applying, and Deleting IP Presets topic.
  • Added new Example IP Preset File (.qprs) topic.
  • Revised Customizing IP Presets topic for board-aware features.
  • Added new Defining Preset Pin Assignments section.
  • Revised Creating a New FPGA Design Project for board-aware features.
  • Added Using the Board-Aware Flow topic.
  • Added Creating a New Project from a Design Example topic.
  • Added Family, Device & Board Settings topic.
  • Added Accessing Pre-Installed Design Examples topic.
  • Added Accessing Online Design Examples topic.
  • Added Accessing Downloaded Design Examples topic.
  • Added Internet Connectivity Options topic.
  • Added Design Examples Options topic.
  • Added Specifying a Target Board for the Project topic.
2022.06.20 22.2
  • Added new Top FAQs navigation to document cover.
  • Revised Introduction to add FPGA definition and device selection footnote.
  • Added new FPGA Basic Design Prerequisites topic.
  • Added new Experiment with a Design Example topic.
  • Removed obsolete Simultaneous Switching Noise Analysis topic from this basic discussion.
2022.03.28 22.1
  • Added information about Power and Thermal Calculator in Plan for Device Power Consumption.
  • Removed references to obsolete Advisors from Optimizing Project Settings topic.
  • Added Viewing Synthesis Warning Messages topic.
  • Removed the topic Automated Problem Reports.
2021.10.04 21.3
  • Added support for Questa*-Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
  • Updated Quartus® Prime Pro Edition IP Version Upgrade Paths figure for latest versions.
2021.06.21 21.2
  • Added Version-Compatible Compilation Database Support table.
  • Added "Promoting Critical Warnings to Errors" topic.
2021.03.29 21.1
  • Enhanced Simulating Intel FPGA Designs topic with screenshot, links, and additional contextual details.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Revised Using the EDA Netlist Writer wording for clarity.
  • Added "Creating Database-Only Archives" topic.
  • Added "Promoting Critical Warnings to Errors" topic
2020.11.09 20.3
  • Revised "Introduction to Intel FPGA IP Cores" topic to include Bridges and Adapters and Intel FPGA Interconnect categories in IP Catalog. Updated IP Catalog image.
  • Revised wording of "Intel FPGA IP Versioning" topic for clarity.
  • Added screenshot to "Checking the IP License Status" topic.
  • Added "IP Version Upgrade Paths" diagram to "Upgrading IP Cores" topic.
  • Updated IP Port Differences Report image in "Troubleshooting IP or System Upgrade" topic.
2020.09.28 20.3
  • Updated GUI screenshot in Introduction.
  • Updated "Back-Annotate Optimized Assignments" for support of pins, clocks, RAMs, and DSPs.
2020.05.01 20.1
  • Added note about .qar file requirements to "Design Guidelines for Component Instances" topic.
2019.09.30 19.3
  • Added compilation support for Agilex™ 7 devices.
  • Added "Checking the IP License Status" topic.
  • Added details to "Support for the IEEE 1735 Encryption Standard."
  • Added Intel® FPGA IP Versioning" topic.
  • Added "Disabling Automated Problem Reports" topic.
  • Added "Suppressing Messages" topic.
2019.05.13 18.1
  • Added archives topic.
  • Updated the keyname and added --help information to "Support for the IEEE 1735 Encryption Standard."
2018.10.24 18.1
  • Updated information about obtaining IEEE 1735 Encryption key.
2018.09.24 18.1
  • Added screenshot of Quartus® Prime Pro Edition GUI.
  • Moved information about specifying the target board to "Specifying the Target Device or Board" in Managing Projects chapter.
  • Retitled "Creating Design Specifications" to "Create a Design Specification and Test Plan."
  • Retitled "Selecting Intellectual Property Cores" to "Plan for Intellectual Property Cores."
  • Retitled "Using Standard Interfaces" to "Plan for Standard Interfaces." Corrected references to Platform Designer.
  • Retitled "Device Selection" to "Plan for the Target Device." Updated this content to correct Platform Designer names.
  • Moved "Setting Pin Assignments" to Managing Projects chapter as "Generating Pin Assignments for a Target Board."
  • Retitled "Estimating Power" to "Plan for Device Power Consumption." Reorganized this topic into sections for EPE and Power Analyzer.
  • Added link to "Simulator Support, Third-Party Simulation User Guide
  • Retitled "Planning for Device Programming or Configuration" to "Plan for Device Programming"
  • Retitled "Selecting Third-Party EDA Tools" to "Plan for other EDA Tools."
  • Retitled "Planning for On-Chip Debugging Tools" to "Plan for On-Chip Debugging Tools."
  • Retitled Design Planning with the Intel Quartus Prime Software to Design Planning
  • Added information about removing assignments from the qsf file that point to legacy output files.
  • Added statement that the Quartus® Prime software installer does not support spaces in the installation path.
  • Added "Intel FPGA IP Best Practices" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter of Getting Started User Guide.
  • Subdivided "Exporting, Archiving, and Migrating Projects" into separate sections.
  • Described migration of full chip database in "Exporting a Version-Compatible Compilation Database" topic.
  • Described automated .qdb partition export in "Exporting a Design Partition" topic.
  • Added "Viewing Quartus Database File Information" topic.
  • Added "Specifying the Target Device or Board" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter.
  • Moved "IP Core Best Practices" topic to Introduction to Intel FPGA IP Cores chapter.
  • Moved "Factors Affecting Compilation Results" topic to Design Compilation: Intel Quartus Prime Pro Edition User Guide.
2018.05.07 18.0
  • Initial release as separate chapter of Getting Started User Guide. Separated Migrating to Quartus® Prime Pro Edition as independent chapter in user guide.
  • Initial release as separate chapter of Getting Started User Guide. Separated Design Planning as independent chapter in user guide.
  • Initial release as separate chapter of Getting Started User Guide. Separated Introduction to Intel® FPGA IP Cores as independent chapter in user guide.
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
  • Added note about Generate Combined Simulator Setup Scripts command limitations.
  • Added information about generation of simulation files for Xcelium*
  • Initial release as chapter of Getting Started User Guide.
  • Revised "Exporting a Design Partition" topic to add Include entity-bound SDC files for the selected partition option, to add prerequisite steps, and to remove import step covered in separate topic.
  • Changed title of "Managing Team-Based Designs" to "Exporting, Archiving, and Migrating Projects" and updated content.
  • Changed title of "Migrating Compilation Results Across Software Versions" to "Exporting the Compilation Database" and updated content.
  • Changed title of "Exporting the Results Database" to "Exporting a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Importing the Results Database" to "Importing a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Cleaning the Project Database" to "Cleaning the Project Compilation Database."
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
2017.11.06 17.1
  • Described Quartus® Prime tool name updates for Platform Designer (Qsys), Interface Planner (BluePrint), Timing Analyzer (TimeQuest), Eye Viewer (EyeQ), and Intel® Advanced Link Analyzer (Advanced Link Analyzer).
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
  • Revised product branding for Intel® standards.
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
2017.05.08 17.0
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
  • Added reference to Block-Based Design Flows.
  • Removed procedure on manual dynamic synthesis report generation. The Compiler automatically generates dynamic synthesis reports when enabled.
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
  • Added note that IP core encryption is supported only in Quartus® Prime Pro Edition.
  • Revised product branding for Intel® standards.
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Added reference to Partial Reconfiguration support.
  • Added to list of Quartus® Prime Standard Edition features unsupported by Quartus® Prime Pro Edition.
  • Added topic on Safe State Machine encoding.
  • Described unsupported Quartus® Prime Standard Edition physical synthesis options.
  • Removed deprecated Per-Stage Compilation (Beta) Compilation Flow.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
  • Implemented Intel rebranding.
  • Described unsupported Quartus® Prime Standard Edition physical synthesis options.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
  • Removed references to .qsys file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Added references to .ip file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Updated IP Core Generation Output files list and diagram.
  • Indicated distinctions between Quartus® Prime Pro Edition and Quartus® Prime Standard Edition features.
  • Added Support for IP Core Encryption topic.
2016.05.03 16.0
  • Removed software beta status and revised feature set.
  • Added topic on Safe State Machine encoding.
  • Added Generating Dynamic Synthesis Reports.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Added description of Fitter Plan, Place and Route stages, reporting, and optimization.
  • Added Per-Stage Compilation (Beta) Compilation Flow.
  • Added Platform Designer information.
  • Added OpenCL and Signal Tap with routing preservation as unique Pro Edition features.
  • Clarified limitations for multiple Logic Lock instances in the same region.
  • Added topic on Safe State Machine encoding.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Clarified limitations for multiple Logic Lock instances in the same region.
2015.11.02 15.1
  • First version of document.
Level Two Title